User Manual

9 LSS-Sh12
Gelb/Rot2
Yellow/Red2
Grün/Weiß
Green/White
Rot/Rot1
Red/Red1
Gleisanschluss
Track input
Widerstände integriert!
Resistors integrated!
Pluspol (Anode)
Ground (Anode)
Sh0 (DB)/Lsp-Hsp (DR) Standard. Adresse 1 „rechts“
Sh0 (DB)/Lsp-Hsp (DR)
Standard. Address 1 “right”
Sh1 (DB)/Ra12 (DR) Standard. Adresse 1 „links“
Sh1 (DB)/Ra12 (DR) Standard. Address 1 „left“
Hp0+Ra12 (DR) Wenn CV49 Bit 7 = 1 (Adresse 2)
Hp0+Ra12 (DR)
If CV49 Bit 7 = 1 (address 2)