Product Info

14
2.10 Pin Layout and Descriptions
Figure 3 Pin layout: top view
1SC
Pin
No
ModulePinName ALT12
50IC
PinNo
ALT1250ICSymbolPin
Name
Type Input/
Output
Reset
Value
IO
Domain/
Supply
Description
1 DEBUG_RSTN P4 DEBUG_RSTN Digital I/O PU VDDIO Reserved (No Connection)
2 DEBUG_SEL M4 DEBUG_SEL/
GPIO31
Digital I/O PD VDDIO Reserved (No Connection)
3 EJ_TDO N5 EJ_TDO/
GPIO22
Digital I/O PU VDDIO Reserved (No Connection)
4 EJ_TRST J5 EJ_TRST/
GPIO20
Digital I/O PD VDDIO Reserved (No Connection)
5 PMU_AT_IN R3 PMU_AT_IN Analog I VRTC Anti-tamper input; short to GND
if not used
6 PMU_WAKEUP P2 PMU_WAKEUP Analog I VRTC Device Wakeup active high;
Device Wake-Up
7 VDD_RF L1 PMU_VO_RF Power O MIPI RFFE VIO (antenna tuning)
8 VSIM R1 PMU_VO_SIM Power O SIM LDO output
9 VDD_AUX T2 PMU_VO_AUX_LDO Power O SC2 LDO output
10 VDD_XO N1 PMU_VO_XO Power O Reserved (No Connection)
11 SIMIO M10 SC_IO/
GPIO14
Digital I/O PD VDDIO SIM Data 1.8V
12 I2C1_SDA H2 I2C1_SDA/
SPIS_MRDY/
PWM 3/
MCU_I2C1_SDA/
MCU_FLA SH1_SCK/
UART0_RI/
MCU_S PIM1_CLK_A/
MCU_PWM3/
GPIO44
Digital I/O PU VDDIO Reserved (No Connection)