Datasheet

SCA100T Series
VTI Technologies Oy Subject to changes 6/18
www.vti.fi Doc. nr. 8261800 Rev.A
1.7 Electrical Connection
If the SPI interface is not used SCK (pin1), MISO (pin3), MOSI (pin4) and CSB (pin7) must be left
floating. Self-test can be activated applying logic “1” (positive supply voltage level) to ST_1 or
ST_2 pins (pins 10 or 9). Self-test must not be activated for both channels at the same time. If ST
feature is not used pins 9 and 10 must be left floating or connected to GND. Inclination signals are
provided from pins OUT_1 and OUT_2.
1
2
3
4
5
67
8
9
10
11
12SCK
Ext_C_1
MISO
MOSI
OUT_2
VSS CSB
Ext_C_2
ST_2
ST_1/Test_in
OUT_1
VDD
Figure 3. SCA100T electrical connection
No. Node I/O Description
1 SCK Input Serial clock
2 NC Input No connect, left floating
3 MISO Output Master in slave out; data output
4 MOSI Input Master out slave in; data input
5 Out_2 Output Y axis Output (Ch 2)
6 GND Supply Ground
7 CSB Input Chip select (active low)
8 NC Input No connect, left floating
9 ST_2 Input Self test input for Ch 2
10 ST_1 Input Self test input for Ch 1
11 Out_1 Output X axis Output (Ch 1)
12 VDD Supply Positive supply voltage (+5V DC)
1.8 Typical Performance Characteristics
Typical offset and sensitivity temperature dependencies of the SCA100T are presented in following
diagrams. These results represent the typical performance of SCA100T components. The mean
value and 3 sigma limits (mean ± 3× standard deviation) and specification limits are presented in
following diagrams. The 3 sigma limits represents 99.73% of the SCA100T population.
SCK
MISO
MOSI
OUT_2
GND
VDD
OUT_1
ST_1
ST_2
CSB