Datasheet

SCA100T Series
VTI Technologies Oy Subject to changes 5/18
www.vti.fi Doc. nr. 8261800 Rev.A
CSB
SCK
MOSI
MISO
T
LS1
T
CH
T
HOL
T
SET
T
VAL1
T
VAL2
T
LZ
T
LS2
T
LH
MSB in
MSB out
LSB in
LSB outDATA out
DATA in
T
CL
1.6 SPI Interface Timing Specifications
Parameter Conditions Symbol Min. Typ. Max. Unit
Terminal CSB, SCK
Time from CSB (10%)
to SCK (90%)
T
LS1
120 ns
Time from SCK (10%)
to CSB (90%)
T
LS2
120 ns
Terminal SCK
SCK low time Load
capacitance at
MISO < 2 nF
T
CL
1
µs
SCK high time Load
capacitance at
MISO < 2 nF
T
CH
1
µs
Terminal MOSI, SCK
Time from changing MOSI
(10%, 90%) to SCK (90%).
Data setup time
T
SET
30 ns
Time from SCK (90%) to
changing MOSI (10%,90%).
Data hold time
T
HOL
30 ns
Terminal MISO, CSB
Time from CSB (10%) to stable
MISO (10%, 90%).
Load
capacitance at
MISO < 15 pF
T
VAL1
10 100 ns
Time from CSB (90%) to high
impedance state of
MISO.
Load
capacitance at
MISO < 15 pF
T
LZ
10 100 ns
Terminal MISO, SCK
Time from SCK (10%) to stable
MISO (10%, 90%).
Load
capacitance at
MISO < 15 pF
T
VAL2
100 ns
Terminal CSB
Time between SPI cycles, CSB at
high level (90%)
T
LH
15
µs
When using SPI commands
RDAX, RDAY, RWTR: Time
between SPI cycles, CSB at high
level (90%)
TLH 150
µs
Figure 2. Timing diagram for SPI communication