Zynq-7000 All Programmable SoC PCB Design Guide UG933 (v1.
Revision History The following table shows the revision history for this document. Date Version Revision 06/04/2012 1.0 Initial Xilinx release. 06/06/2012 1.1 Corrected format issue. 08/29/2012 1.2 Updated Table 3-1 and Table 3-2 for additional devices/packages. Added 680 µF capacitor specification to Table 3-3. 10/11/2012 1.2.1 Corrected document number (changed UG993 to UG933). 11/05/2012 1.2.2 Corrected sizing problem in PDF (no content change). 02/12/2013 1.
Date Version Revision 12/04/2013 1.6 Changed “DDR3” to “DDR3/3L” throughout document. Updated capacitor quantities and packages in Table 3-1 and Table 3-2. Updated capacitor specifications in Table 3-3. Updated descriptions for VCCPINT – PS Internal Logic Supply and VCCPAUX – PS Auxiliary Logic Supply. Deleted “Capacitor Consolidation Rules” section. Modified next-to-last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference Voltage. Added paragraph preceding Table 5-5 and updated Table 5-5.
Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 1: Introduction About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 6: Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Differences between XC7Z030-SBG485 and XC7Z015-CLG485 Devices . . . . . . . . . . . . . . . . . . . . . . 69 Appendix A: Additional Resources and Legal Notices Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction About This Guide This guide provides information on PCB design for the Zynq®-7000 All Programmable SoC (AP SoC), with a focus on strategies for making design decisions at the PCB and interface level. This Zynq-7000 All Programmable SoC PCB Design Guide, part of an overall set of documentation on the Zynq-7000 AP SoC, is available on the Xilinx website at www.xilinx.com/zynq.
Chapter 2 PCB Technology Basics Introduction Printed circuit boards (PCBs) are electrical systems, with electrical properties as complicated as the discrete components and devices mounted to them. The PCB designer has complete control over many aspects of the PCB; however, current technology places constraints and limits on the geometries and resulting electrical properties.
Chapter 2: PCB Technology Basics Traces A trace is a physical strip of metal (usually copper) making an electrical connection between two or more points on an X-Y coordinate of a PCB. The trace carries signals between these points. Planes A plane is an uninterrupted area of metal covering the entire PCB layer. A planelet, a variation of a plane, is an uninterrupted area of metal covering only a portion of a PCB layer. Typically, a number of planelets exist in one PCB layer.
Chapter 2: PCB Technology Basics Lands For the purposes of soldering surface mount components, pads on outer layers are typically referred to as lands or solder lands. Making electrical connections to these lands usually requires vias. Due to manufacturing constraints of PTH technology, it is rarely possible to place a via inside the area of the land. Instead, this technology uses a short section of trace connecting to a surface pad.
Chapter 2: PCB Technology Basics Z-direction spacing of signal trace layers to reference plane layers (defined by total board thickness and number of board layers) is a defining factor in trace impedance.Trace width (defined by AP SoC package ball pitch and PCB via manufacturing constraints) is another factor in trace impedance. A designer often has little control over trace impedance in area of the via array beneath the AP SoC.
Chapter 2: PCB Technology Basics Return Currents An often neglected aspect of transmission lines and their signal integrity is return current. It is incorrect to assume that a signal trace by itself forms a transmission line. Currents flowing in a signal trace have an equal and opposite complimentary current flowing in the reference plane beneath them.
Chapter 3 Power Distribution System Introduction This chapter documents the power distribution system (PDS) for Zynq-7000 AP SoC devices, including decoupling capacitor selection, placement, and PCB geometries. A simple decoupling method is provided for each device. Basic PDS design principles are covered, as well as simulation and analysis methods.
Chapter 3: Power Distribution System the quantity per I/O bank. Device performance at full utilization is equivalent across all devices when using these recommended networks. Table 3-1 and Table 3-2 do not provide the decoupling networks required for the GTX and GTP transceiver power supplies. For this information, refer to UG476, 7 Series FPGAs GTX/GTH Transceivers User Guide and UG482, 7 Series FPGAs GTP Transceivers User Guide.
Chapter 3: Power Distribution System Table 3-1: Required PCB Capacitor Quantities per Device (PL) VCCBRAM VCCINT Package Device FFG1156 Z-7100 680 330 100 µF µF µF 3 0 4.7 0.47 100 µF µF µF 0 2 0 2 VCCAUX 47 µF 4.7 µF 0.47 µF 47 µF 0 4 8 1 4.7 0.47 µF µF 0 VCCO per Bank(3)(4) Bank 0 VCCAUX_IO 0 47 µF 4.7 µF 0.47 µF 47 µF or 100 µF 4.7 µF 0.47 µF 47 µF 1 0 0 1 0 0 1 Notes: 1. PCB Capacitor specifications are listed in Table 3-3. 2.
Chapter 3: Power Distribution System Table 3-2: Required PCB Capacitor Quantities per Device (PS) (Cont’d) VCCPAUX(1) VCCPINT Package Device 100 4.7 0.47 100 FFG1156 Z-7100 VCCO_DDR VCCO_MIO0 VCCPLL(2)(3) VCCO_MIO1 µF µF µF µF 4.7 µF 0.47 µF 100 µF 4.7 µF 0.47 µF 100 µF 4.7 µF 0.47 µF 100 µF 4.7 µF 0.47 µF 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 Notes: 1. See VCCPAUX – PS Auxiliary Logic Supply, page 51 for layout guidelines. 2.
Chapter 3: Power Distribution System Table 3-3: PCB Capacitor Specifications (Cont’d) Ideal Value Value Range(1) Body Size(2) 0.47 µF C > 0.47 µF 0603 Type 2-Terminal Ceramic X7R or X5R ESL Maximum ESR Range(3) Voltage Rating(4) Suggested Part Number 0.5 nH 1 mΩ < ESR < 20 mΩ 6.3V GRM188R70J474KA01 Notes: 1. Values can be larger than specified. 2. Body size can be smaller than specified. 3. ESR must be within the specified range. 4. Voltage rating can be higher than specified.
Chapter 3: Power Distribution System inches of the device’s outer edge is acceptable. The 0.47 µF capacitors should be placed as close to the AP SoC as possible, within 0.5 inches of the outer edge. The capacitor mounting (solder lands, traces, and vias) should be optimized for low inductance. Vias should be butted directly against the pads. Vias can be located at the ends of the pads (see Figure 3-1B), but are more optimally located at the sides of the pads (see Figure 3-1C).
Chapter 3: Power Distribution System supply, often referred to as ripple voltage. Most digital devices, including all Zynq-7000 AP SoC devices, require that VCC supplies not fluctuate more than the specifications documented in the device data sheet. The power consumed by a digital device varies over time and this variance occurs on all frequency scales, creating a need for a wide-band PDS to maintain voltage stability.
Chapter 3: Power Distribution System For example, if current demand in the device increases in a few picoseconds, the voltage at the device sags by some amount until the capacitors can supply extra charge to the device. If current demand in the device maintains this new level for many milliseconds, the voltage-regulator circuit, operating in parallel with the decoupling capacitors, replaces the capacitors by changing its output to supply this new level of current.
Chapter 3: Power Distribution System moves at a different rate. Because momentum (stored magnetic-field energy) is associated with this charge, some amount of time and energy is required to slow down or speed up the charge flow. The greater the inductance, the greater the resistance to change, and the longer the time required for the current level to change. A voltage develops across the inductance as this change occurs.
Chapter 3: Power Distribution System If tantalum capacitors are not available or cannot be used, low-ESR, low-inductance electrolytic capacitors can be used, provided they have comparable ESR and ESL values. Other new technologies with similar characteristics are also available (Os-Con, POSCAP, and Polymer-Electrolytic SMT). A real capacitor of any type then not only has capacitance characteristics but also inductance and resistance characteristics. Figure 3-4 shows the parasitic model of a real capacitor.
Chapter 3: Power Distribution System As different capacitor values are selected in the same package, the capacitive curve moves up and down against the fixed inductance curve, as shown in Figure 3-6. X-Ref Target - Figure 3-6 Z Value at F2 is Equal 0805 0.47 μF Inductance (Z) 0805 4.
Chapter 3: Power Distribution System plane, up through one via, through the connecting trace to the land, through the capacitor, through the other land and connecting trace, down through the other via, and into the other plane, as shown in Figure 3-7.
Chapter 3: Power Distribution System Plane Inductance Some inductance is associated with the PCB power and ground planes. The geometry of these planes determines their inductance. Current spreads out as it flows from one point to another (due to a property similar to skin effect) in the power and ground planes. Inductance in planes can be described as spreading inductance and is specified in units of henries per square.
Chapter 3: Power Distribution System between power and ground planes decreases, the value of this capacitance increases. Capacitance per square inch is shown in Table 3-4. However, the amount of capacitance arising from these PCB power-ground plane pairs is generally inconsequential, given the substrate decoupling capacitors present in Zynq-7000 AP SoC devices.
Chapter 3: Power Distribution System • Both mounting inductances are reduced by placing power planes close to the PCB stackup’s top half and placing the capacitors on the top surface (reducing the capacitor’s via length). • If power planes are placed in the PCB stackup’s bottom half, the capacitors must be mounted on the PCB backside. In this case, AP SoC mounting vias are already long, and making the capacitor vias long (by coming down from the top surface) is a bad practice.
Chapter 3: Power Distribution System • Ceramic chip capacitors with a lower ESR, generally have a very narrow effective frequency band. An ideal capacitor only has a capacitive characteristic, whereas real non-ideal capacitors also have a parasitic inductance (ESL) and a parasitic resistance (ESR). These parasitics work in series to form an RLC circuit (Figure 3-4). The RLC circuit’s resonant frequency is the capacitor’s self-resonant frequency.
Chapter 3: Power Distribution System L MOUNT = 0.8 nH (based on PCB mounting geometry) To determine the effective in-system parasitic inductance (L IS), add the via parasitics: L IS = L SELF + L MOUNT = 0.9 nH + 0.8 nH L IS = 1.7 nH Equation 3-3 The values from the example are used to determine the mounted capacitor resonant frequency (FRIS).
Chapter 3: Power Distribution System Capacitor Placement Background To perform the decoupling function, capacitors should be close to the device being decoupled. Increased spacing between the AP SoC and decoupling capacitor increases the current flow distance in the power and ground planes, and it often increases the current path’s inductance between the device and the capacitor.
Chapter 3: Power Distribution System Another delay of the same duration occurs when the compensation current from the capacitor flows to the AP SoC. For any transient current demand in the AP SoC, a round-trip delay occurs before any relief is seen at the AP SoC. • Negligible energy is transferred to the AP SoC with placement distances greater than one quarter of a demand frequency’s wavelength. • Energy transferred to the AP SoC increases from 0% at one-quarter of a wavelength to 100% at zero distance.
Chapter 3: Power Distribution System Unconnected VCCO Pins In some cases, one or more I/O banks in an AP SoC are not used (for example, when an AP SoC has far more I/O pins than the design requires).
Chapter 3: Power Distribution System PDS Measurements Measurements can be used to determine whether a PDS is adequate. PDS noise measurements are a unique task, and many specialized techniques have been developed. This section describes the noise magnitude and noise spectrum measurements. Noise Magnitude Measurement Noise measurement must be performed with a high-bandwidth oscilloscope (minimum 3 GHz oscilloscope and 1.5 GHz probe or direct coaxial connection) on a design running realistic test patterns.
Chapter 3: Power Distribution System • Place the oscilloscope in infinite persistence mode to acquire all noise over a long time period (many seconds or minutes). If the design operates in many different modes, using different resources in different amounts, these various conditions and modes should be in operation while the oscilloscope is acquiring the noise measurement. • Place the oscilloscope in averaging mode and trigger on a known aggressor event.
Chapter 3: Power Distribution System X-Ref Target - Figure 3-9 UG933_c3_09_032811 Figure 3-9: Infinite Persistence Measurement of Same Supply The measurement shown in Figure 3-8 and Figure 3-9 represents the peak-to-peak noise. If the peak-to-peak noise is outside the specified acceptable voltage range, the decoupling network is inadequate or a problem exists in the PCB layout. 3.0.
Chapter 3: Power Distribution System Excessive noise at a certain frequency indicates a frequency where the PDS impedance is too high for the device’s transient current demands. Using this information, the designer can modify the PDS to accommodate the transient current at the specific frequency. This is accomplished by either adding capacitors with effective frequencies close to the noise frequency or otherwise lowering the PDS impedance at the critical frequency.
Chapter 3: Power Distribution System X-Ref Target - Figure 3-10 UG933_c3_10_032811 Figure 3-10: Screenshot of Spectrum Analyzer Measurement of VCCO Optimum Decoupling Network Design If a highly optimized PDS is needed, measurements and simulations of a prototype system can inform the PDS design. Using knowledge of the noise spectrum generated by the prototype system along with knowledge of the system’s power system impedance, the unique transient current of the design can be determined and accommodated.
Chapter 3: Power Distribution System specially designed capacitor network can accommodate the specific design’s transient current. Troubleshooting In some cases the proper design work is done up-front, but noise problems still exist. This next section describes possible issues and suggested resolution methods.
Chapter 3: Power Distribution System Other improvements of geometry are via-in-pad (via under the solder land), not shown, and via-beside-pad (vias straddle the lands instead of being placed at the ends of the lands). Double vias also improve connecting trace geometry and capacitor land geometry. Exceptionally thick boards (> 3.2 mm or 127 mils) have vias with higher parasitic inductance.
Chapter 4 SelectIO Signaling Introduction The Zynq-7000 AP SoC SelectIO resources are the general-purpose I/O and its various settings. With numerous I/O standards and hundreds of variants within these standards, these SelectIO resources offer a flexible array of choices for designing I/O interfaces. This chapter provides some strategies for choosing I/O standard, topography, and termination, and offers guidance on simulation and measurement for more detailed decision making and verification.
Chapter 4: SelectIO Signaling the V IL threshold, the state is considered Low. TTL is one common example of a single-ended I/O standard. To reach higher interface speeds and increase noise margin, some single-ended I/O standards rely on a precise dedicated local reference voltage other than GND. HSTL and SSTL are examples of I/O standards that rely on a VREF to resolve logic levels. V REF can be thought of as a fixed comparator input.
Chapter 4: SelectIO Signaling Some I/O standards have attributes to control drive strength and slew rate, as well as the presence of weak pull-up or pull-down and weak-keeper circuits (not intended for use as parallel termination). Drive strength and slew rate can be used to tune an interface for adequate speed while not overdriving the signals. Weak pull-ups, weak pull-downs, and weak keepers can be used to ensure a known or steady level on a floating or 3-stated signal.
Chapter 4: SelectIO Signaling The SelectIO standards can be used in countless topographies depending on the requirements of the system. SelectIO drivers and receivers adhering to a standard (SSTL, LVCMOS, etc.) either can be used according to the letter of the standard (published by a standards body such as EIA/TIA or JEDEC) or they can be mixed and matched with drivers or receivers from another standard or hybrid I/O.
Chapter 4: SelectIO Signaling X-Ref Target - Figure 4-2 RO = 25Ω RS = Z0 – R0 = 25Ω Z0 = 50Ω UG933_c4_02_031711 Figure 4-2: Series-Terminated Unidirectional, Point-to-Point Topography X-Ref Target - Figure 4-3 LVDCI RO = RVRN = RVRP > Z0 = 50Ω Z0 = 50Ω UG933_c4_03_031711 Figure 4-3: DCI-Controlled Impedance Driver Unidirectional, Point-to-Point Topography X-Ref Target - Figure 4-4 LVCMOS (DRIVE = 6, SLEW = FAST) RO ≈ Z0 ~ 50Ω Z0 = 50Ω UG933_c4_04_031711 Figure 4-4: “Weak Driver” Unidirectional,
Chapter 4: SelectIO Signaling Parallel termination can be less desirable than series termination or controlled-impedance drivers because it dissipates more power. This trade-off must be weighed against other trade-offs to determine the optimum termination topography for an interface. X-Ref Target - Figure 4-5 VCCO = 2.5V RPT = 2 x Z0 = 100Ω RO = 25Ω Z0 = 50Ω VTTEQ = 1.
Chapter 4: SelectIO Signaling The SSTL standards tend to not have rigid requirements for termination topology. Rather, the JEDEC specifications provide example termination techniques that tend to be the commonly used topographies. The “SelectIO Resources” chapter of UG471, 7 Series FPGAs SelectIO Resources User Guide provides example termination techniques for each of the I/O standards, including the SSTL standards, for the purpose of providing a good starting point for consideration.
Chapter 4: SelectIO Signaling X-Ref Target - Figure 4-6 Input 4 Output Main Transmission Line Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω length < 8mm Z0 = 50Ω length < 8mm Z0 = 50Ω length < 8mm VCCO 2 x Z0 = 100Ω Input 1 Input 2 Input 3 2 x Z0 = 100Ω UG933_c4_06_031711 Figure 4-6: Basic Multi-Drop Topography The main transmission line should be kept as short as possible.
Chapter 4: SelectIO Signaling topography is point-to-point or multi-point defines important aspects of the interface that determine which termination strategies are appropriate and which are not. Bidirectional Point-to-Point Topographies The simplest bidirectional topography is point to point. That is, there are two transceivers connected by a transmission line. Because bidirectional interfaces need to operate equally well in both directions, symmetry of the topography is desirable.
Chapter 4: SelectIO Signaling X-Ref Target - Figure 4-9 RO = RVRN = RVRP ≈ Z0 = 50Ω LVDCI_15 Z0 = 50Ω RO = RVRN = RVRP ≈ Z0 = 50Ω LVDCI_15 UG933_c4_09_032411 Figure 4-9: DCI Controlled Impedance Bidirectional Point-to-Point Topography X-Ref Target - Figure 4-10 RO = 0.5 x RVRN = 0.5 x RVRP ≈ Z0 = 50Ω LVDCI_DIV2_15 Z0 = 50Ω VREF RO = 0.5 x RVRN = 0.
Chapter 4: SelectIO Signaling external precision resistors placed on the VRN and VRP pins for that bank, the resulting controlled output impedance for that bank would be 50Ω.
Chapter 4: SelectIO Signaling Table 4-3: Example I/O Interface Types for Bidirectional Point-to-Point I/O Topographies SSTL15 DCI SSTL18 CLASS II SSTL18 CLASS II DCI HSTL CLASS II HSTL CLASS II DCI LVTTL and LVCMOS do not specify any canonical termination method. Series termination is not recommended for bidirectional interfaces. Parallel termination and weak drivers, however, are both appropriate. LVDCI and HSLVDCI both implicitly use controlled-impedance driver termination.
Chapter 5 Processing System (PS) Power and Signaling Power Zynq-7000 AP SoC devices are divided into several power domains. Figure 5-1 shows an overview of those domains. X-Ref Target - Figure 5-1 Processing System (PS) Programmable Logic (PL) VCCPINT VCCINT VCCPAUX VCCAUX VCCPLL VCCO_MIO0 VCCO_DDR VCCO_MIO1 VCCO0 VCCO1 VCCOn UG933_c5_01_051212 Figure 5-1: Power Domains Main Power Supplies VCCPINT – PS Internal Logic Supply VCCPINT is a 1.
Chapter 5: Processing System (PS) Power and Signaling capacitor to the adjacent VCCPAUX and GND BGA vias. This supply can be combined with VCCAUX if the system does not require the PL supply to be powered down independent of the PS. VCCPLL – PS PLL Supply VCCPLL is a 1.8V nominal supply that provides power to the three PS PLLs and additional analog circuits. It can be powered separately or derived from the VCCPAUX supply.
Chapter 5: Processing System (PS) Power and Signaling X-Ref Target - Figure 5-3 UG933_c5_10_020713 Figure 5-3: Filtering Circuit Layout PS DDR Power Supplies VCCO_DDR – PS DDR I/O Supply VCCO_DDR is a 1.2V–1.8V nominal supply that supplies the DDR I/O bank input and output drivers. This supply sources the DDR output drivers, input receivers and termination circuitry. Its requirements are defined by the type of interface (DDR2, DDR3/3L or LPDDR2), memory speed, and the data bus width.
Chapter 5: Processing System (PS) Power and Signaling PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination Voltage PS_DDR_VRN and PS_DDR_VRP provide a reference for digitally controlled impedance (DCI) calibration. For memory types that require termination (DDR2, DDR3) VRP must be pulled Low to GND and VRN needs to be pulled High to VCCO_DDR. For DDR2/3, the resistor value on VRP and VRN should be twice the memory's trace and termination impedance.
Chapter 5: Processing System (PS) Power and Signaling MIO[7] and MIO[8] are dual use pins that are shared with the high-speed QSPI/NAND/SRAM interface signals. Special care needs to be taken to avoid signal integrity issues. CAUTION! If the MIO bank voltage is incorrectly set, the I/O behaves unpredictably and damage might occur. For example, avoid setting the MIO voltage to 3.3V while using HSTL18. Any pull-up resistors should only connect to V CCO_MIO0 .
Chapter 5: Processing System (PS) Power and Signaling PS Clock and Reset PS_CLK – Processor Clock PS_CLK shall be connected to a clock generator providing a 30-60 MHz clock. The clock must be a single-ended LVCMOS signal, using the same voltage level as the VCCO_MIO0 I/O voltage for bank MIO0.
Chapter 5: Processing System (PS) Power and Signaling X-Ref Target - Figure 5-4 VCCO_MIO0 1 2 MIO 20 KΩ 3 GND UG585_c30_03_020713 Figure 5-4: Setting Mode Pins Dynamic Memory Zynq-7000 AP SoC devices support DDR2, DDR3/3L, and LPDDR2 (mobile DDR) dynamic memory. The memory is connected to dedicated pins in I/O Bank 502. This bank has dedicated I/O, termination, and reference voltage supplies. DDR runs at very high speeds and special care need to be taken in board layout to ensure signal integrity.
Chapter 5: Processing System (PS) Power and Signaling Table 5-4: DDR Interface Signal Pins (Cont’d) Pin Name Direction DDR_DQ[31:0] I/O DDR_DM[3:0] O Description Data Data mask DDR_DQS_P[3:0] I/O Differential data strobe positive DDR_DQS_N[3:0] I/O Differential data strobe negative DDR_VRP I/O Used to calibrate input termination DDR_VRN I/O Used to calibrate input termination DDR_VREF[1:0] I/O Reference voltage Unused DDR pins should be connected as shown in Table 5-5.
Chapter 5: Processing System (PS) Power and Signaling X-Ref Target - Figure 5-5 VREF VDDQ VREF VREF VDDQ Addr, Command, Contrl (Addr, we_b, ras_b, cas_b, odt, cs_b) ZYNQ CLK_P CLK_N CKE DRST_B Data Group 0 (dq, dqs, dm) Rdown VDDQ VREF VDDQ VREF VDDQ Addr, Command, Contrl (Addr, we_b, ras_b, cas_b, clk odt, cs_b) VREF VDDQ Addr, Command, Contrl (Addr, we_b, ras_b, cas_b, clk odt, cs_b) Cke Cke rset_b rset_b DDR3 Data Group (dq, dqs, dm) VREF VDDQ VREF VDDQ VTT Addr, Command, Rterm Cont
Chapter 5: Processing System (PS) Power and Signaling X-Ref Target - Figure 5-6 VREF VREF VDDQ VDDQ Data Group 0 (dq, dqs, dm) VREF VDDQ VREF VDDQ VREF Data Group (dq, dqs, dm) VDDQ Data Group VREF (dq, dqs, dm) VDDQ DDR2 DDR2 CLK Addr, Command, Contrl (Addr, cke _P_N we_b, ras_b, cas_b, odt, cs_b) Data Group 1 (dq, dqs, dm) cke CLK Addr, Command, Contrl (Addr, _P_N we_b, ras_b, cas_b, odt, cs_b) Rdown ZYNQ Cke CLK_P CLK_N Rclk VTT Rterm Addr, Command, Contrl (Addr, we_b, ras_b, cas_b,
Chapter 5: Processing System (PS) Power and Signaling X-Ref Target - Figure 5-7 VREF VREF VDDQ VDDQ Data Group 0 (dq, dqs, dm) Data Group 0 (dq, dqs, dm) Data Group 1 (dq, dqs, dm) Data Group 1 (dq, dqs, dm) cke VREF VDDQ VREF VDDQ LPDDR2 zq Addr, Command, Contrl (CA, cs_b) clk Rzq Cke ZYNQ Rdown clk Addr, Command, Contrl (Addr, cs_b) cke clk Addr, Command, Contrl (CA, cs_b) Data Group 2 (dq, dqs, dm) Data Group 0 (dq, dqs, dm) Data Group 3 (dq, dqs, dm) Data Group 1 (dq, dqs, dm) VDDQ
Chapter 5: Processing System (PS) Power and Signaling Table 5-6: DDR Voltage (Cont’d) Voltage LPDDR2 DDR2 DDR3 DDR3L Comments V TT V DDQ /2 V DDQ /2 VDDQ /2 VDDQ /2 PS_DDR_VREF0 PD_DDR_V REF1 VREF V DDQ /2 V DDQ /2 VDDQ /2 VDDQ /2 Use a DDR termination regulator or a resistor voltage divider to generate V TT and VREF DDR Termination For better signal integrity, DDR2 and DDR3 clock, address, command and control signals need to be terminated.
Chapter 5: Processing System (PS) Power and Signaling In addition, DDR signals also require matched trace delays, which include package delays. Table 5-9 shows the recommended delay matching for DDR. Differential traces should be delay matched such that the signal crossing point occurs in the linear region of the rising and falling edges. The skew limits can be increased if the memory interface is not operated at the maximum frequency, and/or if a faster memory device is utilized.
Chapter 5: Processing System (PS) Power and Signaling Note: For PS_DDR_DQxx, ensure that byte lines are kept together. PS_DDR_ADDR0 should always be used. If bits must be omitted for chip select or other functionality, omit upper bit (PS_ADDR14) instead.
Chapter 5: Processing System (PS) Power and Signaling MIO/EMIO IP Layout Guidelines This section lists MIO/EMIO interface-specific layout guidelines. CAN (Controller Area Network) A level shifter must be implemented if using a CAN PHY that operates at 5.0V. Ethernet GEM Depending which RGMII specification the external PHY supports, the TX/RX clocks might need to be delayed on the PCB relative to their respective data and control lines: • • • PHYs that support RGMII v1.
Chapter 5: Processing System (PS) Power and Signaling the Zynq-7000 AP SoC device and SD chip. PCB and package delay skew for SD_DAT[0:3] and SD_CMD relative to SD_CLK should be less than ±50 ps. Asynchronous signals SD_CDn and SD_WPn have no timing relationship to SD_CLK. The Cdn and WPn lines should both be pulled up with their own 50 kΩ resistors to the MIO I/O voltage.
Chapter 5: Processing System (PS) Power and Signaling QSPI The clock, data, and SS lines are recommended to have matched lengths to facilitate meeting setup and hold times. PCB and package delay skew for QSPI_IO[0:3] and QSPI_SS lines relative to QSPI_SCLK should be less than ±50 ps. Keeping the clock and data lines equal provides greater immunity to undesirable setup and hold time effects.
Chapter 5: Processing System (PS) Power and Signaling 1 Fmax3 = -------------------------------------------------------------------------2 × ( Thold flash – TQSPICKOMIN ) Equation 5-3 For Fmax1, TQSPICKOMAX and TQSPIDCK are the respective clock-to-out and setup times of the Zynq-7000 AP SoC device.
Chapter 6 Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices Introduction Package migration across a device family is a common feature among Xilinx devices. The pinout remains consistent, with the biggest difference being more available I/Os in bigger packages. However, a unique case arises when migrating from an XC7Z030-SBG485 device to an XC7Z015-CLG485 device, as there are more significant differences between the devices other than pinout.
Chapter 6: Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices Table 6-1: Key Differences Between XC7Z030-SBG485 and XC7Z015-CLG485 Devices (Cont’d) XC7Z030-SBG485 XC7Z015-CLG485 Bank 112, pin W3 MGTVCCAUX Not Connected Xilinx Design Software Vivado and ISE Vivado Only Functional and Performance Differences The main functional and performance-related difference between the two devices is the programmable logic upon which each is based.
Chapter 6: Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices connected on the XC7Z015-CLG485 device, but that are connected on the XC7Z030-SBG485 device. Software Considerations The Zynq-7000 XC7Z015 device is not supported in the ISE Design Suite and you should not use the Zynq-7000 XC7Z030 device in the SBG485 package in an attempt to migrate to a Zynq-7000 XC7Z015 device in the ISE Design Suite.
Appendix A Additional Resources and Legal Notices Xilinx Resources Product Support and Documentation • For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. • For continual updates, add the Answer Record to your myAlerts.. Device User Guides http://Zynq-7000 AP SoC Product Page http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm Xilinx Design Tools: Release Notes, Installation, and Licensing http://www.xilinx.com/support/index.
Appendix A: Additional Resources and Legal Notices Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.
Appendix A: Additional Resources and Legal Notices ° UG479, Xilinx 7 Series FPGAs DSP48E1 Slice User Guide ° UG480, Xilinx 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide ° UG483, Xilinx 7 Series FPGAs PCB Guide These user guides and additional relevant information can be found on the Xilinx 7 Series product page: http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/f pga/num-7-series.
Appendix A: Additional Resources and Legal Notices Xilinx ISE Design Suite http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/i se_design_suite.html Xilinx Embedded Development Kit (EDK) http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/ embedded_development_kit__edk.html ChipScope Pro Documentation http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/ chipscope_pro.html Xilinx Problem Solvers http://www.
Appendix A: Additional Resources and Legal Notices ° ARM Debug Interface v5.1 Architecture Specification ° ARM Debug Interface v5.
Appendix A: Additional Resources and Legal Notices terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos. © Copyright 2012–2014 Xilinx, Inc.
