Datasheet

Note 1: See section I
2
C/SMBus Setup and Hold Times – Defi nitions.
Note 2: Monitorable over PMBus Interface.
Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the
fault reappear after restart. See Operating Information for other fault response options.
Note 4: Tsw is the switching period.
Note 5: Within +/-3% of VO
Note 6: See section Soft-start Power Up.
Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals
accuracy will depend on the regulator bandwidth.
Note 8: See section Over Temperature Protection (OTP).
Note 9: See section External Capacitors.
Note 10: See section Initialization Procedure.
Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.
Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.
Note 13: Time for reaching 100% of nominal Vout.
Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.
Note 15: Accuracy here means deviation from ideal output voltage level given by confi gured droop and actual load.
Includes line, load and temperature variations.
Note 16: For current sharing the Output Voltage Delay Time must be reconfi gured to minimum 15 ms.
Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative.
Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled).
Note 19: See sections Dynamic Loop Compensation and Power Good.
Characteristics Conditions Min Typ Max Unit
Over Temperature Protection,
OTP at P2
See Note 8
OTP threshold 120
°C
OTP threshold range PMBus confi gurable -40…+125
°C
OTP hysteresis 25
°C
OTP hysteresis range PMBus confi gurable 0-165
°C
Fault response See Note 3 Automatic restart, 240 ms
V
IL
Logic input low threshold
SYNC, SA0, SA1, SCL, SDA, GCB, CTRL,
VSET
0.8 V
V
IH
Logic input high threshold 2 V
I
IL
Logic input low sink current CTRL 0.6 mA
V
OL
Logic output low signal level
SYNC, SCL, SDA, SALERT, GCB, PG
0.4 V
V
OH
Logic output high signal level 2.25 V
I
OL
Logic output low sink current 4mA
I
OH
Logic output high source current 2mA
t
set
Setup time, SMBus See Note 1 300 ns
t
hold
Hold time, SMBus See Note 1 250 ns
t
free
Bus free time, SMBus See Note 1 2 ms
C
p
Internal capacitance on logic pins 10 pF
Initialization time See Note 10 40 ms
Output Voltage
Delay Time
See Note 6
Delay duration See Note 16 10
ms
Delay duration range PMBus confi gurable 5-500000
Delay accuracy
turn-on
-0.25/+4 ms
Delay accuracy
turn-off
-0.25/+4 ms
Output Voltage
Ramp Time
See Note 13
Ramp duration 10
ms
Ramp duration range PMBus confi gurable 0-200
Ramp time accuracy
100 µs
Current sharing operation 20 %
VTRK Input Bias Current V
VTRK
= 5.5 V 110 200 µA
VTRK Tracking Ramp Accuracy (V
O
- V
VTRK
)
100% tracking, see Note 7 -100 100 mV
Current sharing operation
2 phases, 100% tracking
V
O
= 1.0 V, 10 ms ramp
±100 mV
VTRK Regulation Accuracy (V
O
- V
VTRK
)
100% Tracking -1 1 %
Current sharing operation
100% Tracking
-2 2 %
Current difference between products in a current sharing group
Steady state operation Max 2 x READ_IOUT monitoring accuracy
Ramp-up 4 A
Number of products in a current sharing group 7
Monitoring accuracy
READ_VIN vs V
I
3 %
READ_VOUT vs V
O
1%
READ_IOUT vs I
O
I
O
= 0-50 A, T
P1
= 0 to +95 °C
V
I
= 4.5-14 V, V
O
= 1.0 V
±3.0 A
READ_IOUT vs I
O
I
O
= 0-50 A, T
P1
= 0 to +95 °C
V
I
= 4.5-14 V, V
O
= 0.6-3.3 V
±5.0 A
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
MDC_OKDx-T/50-W12-C.A04 Page 5 of 41
www.murata-ps.com/support