User's Manual

RPT 633
Page 3 - 4 TM1184 Issue 1
Crystal Oscillator
7. The reference oscillator TR11 is of the crystal controlled Colpitts type, operating on
the fundamental frequency of the crystal which is 1/48th of the output frequency for
Bands 1 and 2 and 1/56th of the output frequency for Band 3. The oscillator
frequency is trimmed by VC5. Varactor Diode D8 provides the modulation, The
capacitance of the diode, and therefore the oscillator frequency varies with the
voltage across the diode. The output of the oscillator is buffered by IC8b.
High Stability Version
8. On the high stability version a temperature controlled crystal oven OV1 is fitted
which covers the special high temperature crystal.
Voltage Controlled Oscillator (VCO)
9. Transistor TR2 is a Colpitts oscillator running at half the carrier frequency, the
frequency being determined by L1, C4, C5, C6 and the capacitance of the dual
varactor diode D1. The output of the oscillator is buffered by IC1 and TR4.
Phase Locked Loop (PLL)
10. The VCO output frequency from TR4 is divided by 256 in IC9 and then buffered by
linear amplifiers IC8c and IC8d before being fed to IC7. Within IC7 the signal is
further divided by either 6 (for output frequencies less than 447Mhz) or by 7 by a
programmable divider, the division ratio being set by shorting link LK2, 1-2 equals
divide-by-6 and 2-3 equals divide-by-7. Also, within IC7, the crystal oscillator
frequency is divided by 64 before being fed, together with the VCO signal, to a
phase/ frequency comparator. E.g. for a carrier frequency of 448MHz the crystal
oscillator frequency is 8MHz which gives an input to the comparator of 125kHz. The
VCO is running at 224MHz which is divided by IC9 to give 875kHz and then by IC7
(LK2 2-3) to give 125kHz. The PLL control output is fed out of IC7 at pin 13 and
via loop filter R47, R48, C69, and C70 to the VCO. The filter controls the dynamic
behaviour of the loop, the modulation frequency response and the level of the PLL
reference frequency sidebands. When the PLL has achieved lock it sends a high
in-lock signal from IC7 pin 12, via delay circuit R49, R50, C71 and D5, the buffers
IC8a and IC8f, to forward bias TR5 and TR8. D5 allows C71 to discharge quickly
when the lock fail condition occurs and to charge slowly when the in-lock condition
is restored.