Specifications

PART 3 – Analog SocketModems Chapter 10 – SocketModem (MT5692SMI)
Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342P) 169
MSR – Modem Status Register
(Addr = 6)
The Modem Status Register (MSR) reports current state and change information of the modem. Bits 4-7 supply
current state and bits 0-3 supply change information. The change bits are set to a 1 whenever a control input
from the modem changes state from the last MSR read by the host. Bits 0-3 are reset to 0 when the host reads
the MSR or upon reset.
Whenever bits 0, 1, 2, or 3 are set to a 1, a Modem Status Interrupt (IIR0-IIR3 = 0) is generated.
Bit 7 Data Carrier Detect (DCD)
This bit indicates the logic state of the DCH# (RLSD#) output.
Bit 6 Ring Indicator (RI)
This bit indicates the logic state of the RI# output.
Bit 5 Data Set Ready (DSR)
This bit indicates the logic state of the DSR# output.
Bit 4 Clear to Send (CTS)
This bit indicates the logic state of the CTS# output.
Bit 3 Delta Data Carrier Detect (DDCD)
This bit is set to a 1 when the DCD bit changes state since the host last read the MSR.
Bit 2 Trailing Edge of Ring Indicator (TERI)
This bit is set to a 1 when the RI bit changes from a 1 to a 0 state since the host last read the
MSR.
Bit 1 Delta Data Set Ready (DDSR)
This bit is set to a 1 when the DSR bit has changed since the host last read the MSR.
Bit 0 Delta Clear to Send (DCTS)
This bit is set to a 1 when the CTS bit has changed since the MSR the host last read the MSR.
RBX – RX Buffer (Receiver Buffer Register)
(Addr = 0, DLAB = 0)
The RX Buffer (RBR) is a read-only register at location 0 (with DLAB = 0). Bit 0 is the least significant bit of the
data and is the first bit received.
THR – TX Buffer (Transmitter Holding Register)
(Addr = 0, DLAB = 0)
The TX Buffer (THR) is a write-only register at address 0 when DLAB = 0. Bit 0 is the least significant bit and the
first bit sent.