Specifications

Chapter 3 – SocketModem (MT5634SMI & MT9234SMI)
Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342F) 80
A typical (interrupt driven) write to the RX block is a two-step process. The MMM micro-controller
must first write the 3 error bits to a shadow MMM LSR status register. Next, the micro-controller
writes the data to the RX FIFO and during this write operation, the 3 error bits are directly loaded
from the LSR shadow register into the bits 8-10 of the selected (11 bit-wide) FIFO register. These
error bits represent the parity error, framing error, and break interrupt signals associated with each
data work transmission into the receive FIFO. When the receive FIFO is read, these error bits are
loaded directly into bits 2-4 of the MMM LSR register.
A2 A1 A0 Register Name Register Description Host Access
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
Receive Buffer (RX FIFO)
Transmit Holding (TX FIFO)
Interrupt Enable
Interrupt Identification
FIFO Control
Line Control
Modem Control
Line Status
Modem Status
Scratch pad
DLAB = 0 R only
DLAB = 0 W only
DLAB = 0 R/W
DLAB = X R only
DLAB = X W only
DLAB = X R/W
DLAB = 0 R/W
DLAB = X R only
DLAB = X R only
DLAB = 0 R/W
0
0
1
1
0
0
1
0
0
1
1
0
DLL
DLM
DLX
MCX
LSB of Divisor Latch
MSB of Divisor Latch
Divisor Latch
Status/Control
DLAB = 1 R/W
DLAB = 1 R/W
DLAB = 1 R/W
DLAB = 1 R/W
Note 1* The General Register set is accessible only when DS is a logic 0.
Note 2* The Baud Rate register set is accessible only when DS is a logic 0 and LCR bit-7 is a logic 1.
Time Out Interrupts
The interrupts are enabled by IER bits 0-3. Care must be taken when handling these interrupts.
Following a reset the transmitter interrupt is enabled, the SocketModem will issue an interrupt to
indicate that transmit holding register is empty. This interrupt must be serviced prior to continuing
operations.
The LSR register provides the current singular highest priority interrupt only. A condition can exist
where a higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the
higher pending interrupt will the lower priority interrupt(s) be reflected in the status register.
Servicing the interrupt without investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these interrupts
correctly.
Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER
bit-3). The receiver issues an interrupt after the number of characters received have reached the
programmed trigger level. In this case the MMM FIFO may hold more characters than the
programmed trigger level. Following the removal of a data byte, the user should recheck LSR bit-0
for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time
out counter is reset at the center of each stop bit received or each time the receive holding register
(RHR) is read.