Specifications

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Chapter 3 – SocketModem (MT5634SMI & MT9234SMI)

Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342F) 79

SocketModem Parallel Interface Internal

Registers

The SocketModem parallel interface is a mimic of a 16C550A UART. It is similar to the MIMIC interface used in the

Zilog Z80189. The SocketModem mimic (MMM) takes advantage of this standard interface while replacing the serial

to parallel data transfer with a less complicated parallel to parallel data transfer.

The MMM interface controls an 8-bit parallel data transfer which is typically interrupt driven. Interrupts usually indicate

one or both of two conditions: (1) the receive (RX) FIFO has either reached a trigger level or time-out condition and

needs to be emptied and/or (2) the transmit (TX) FIFO is empty and waiting for more data from the Host. An interrupt

can also be triggered by a change in the modem status register (i.e., loss of carrier) or by the occurrence of errors in

the line status register (overrun, parity, framing, break detect).

In addition to the receive and transmit FIFOs, there are twelve other control/status registers called the MMM register

set which can be accessed through this interface.

Overview

SocketModem MIMIC (MMM) Operation

Data flow through MMM is bi-directional. Simultaneously, data can flow from the host through the

transmit FIFO to the SocketModem controller, and data can flow from SocketModem controller through

the receive FIFO to the Host. In the receive path, 8-bit data is asynchronously received (from the

SocketModem controller) by the receive FIFO where it is stored along with associated three error bits.

The error bits must arrive (via a SocketModem controller I/O write to MMM shadow line status register)

prior to receiving the actual data bits. The error bits are then temporarily stored so they may be written,

with associated data bits, to the 11-bit wide RX FIFO.

After every data write, the RX FIFO write pointer is incremented. RX FIFO trigger levels, data ready

signal, and time-out counter are checked to see if a Host interrupt needs to be sent. The data ready

signal will be activated and MMM sits poised to accept another data word.

We highly recommend the host should read the MMM IIR register to determine the type of interrupt.

Then it might check bit 7 of the LSR to see if there are any errors in the data currently residing in the

receive FIFO. Finally, it will (1) alternately read a data word through the RX FIFO read pointer and the

error bits via the MMM LSR until the FIFO is empty, or (2) read successive data words (knowing there

were no errors in the FIFO) until the trigger count is met.

A similar sequence occurs when data flows in the other direction (from host through transmit FIFO),

except there is no error bit manipulation/checking involved.

FIFO Operation

The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-

0. You can set the receive trigger level via FCR bits 6/7. The receiver FIFO section includes a time-

out function to ensure data is delivered to the external host. An interrupt is generated whenever the

Receive Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has been reached.

Receive (RX) FIFO

The RX FIFO can be configured to be 16 words deep and 11 bits wide. Each word in the RX FIFO

consists of 8 data bits and 3 error bits. The RX block of the MMM contains read and write pointers

and status flag circuitry that need only to be presented with data (for input), reset, read/write control

signals, and read/write clock signals. The RX block of the MMM internally manages the FIFO

problems).

The RX block of the MMM provides data (for output), FIFO full flag, FIFO empty flag, and an almost

full flag which uses an associated predefined trigger level (obtained from the MMM FCR control

by programming bits 6-7 of the FCR control register.