Specifications

Chapter 2 – SocketModem (MT5600SMI & MT5656SMI)
Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342F) 59
SocketModem Parallel Interface
The modem supports a 16550A interface in parallel interface versions. The 16550A interface can operate in FIFO
mode or non-FIFO mode. Non-FIFO mode is the same as the 16450-interface operation. FIFO mode’s unique
operations are described in this chapter.
Overview
The modem emulates the 16450/16550A interface and includes both a 16-byte receiver data first-in first-out
buffer (RX FIFO) and a 16-byte transmit data first-in first-out buffer (TX FIFO).
FIFO Mode Selected
When FIFO mode is selected in the FIFO Control Register (FCR0 = 1), both FIFOs are operative.
Furthermore, when FIFO mode is selected, DMA operation of the FIFO can also be selected (FCR3 =
1).
FIFO Mode Not Selected
When FIFO mode is not selected, operation is restricted to a 16450-interface operation.
Receive Data
Received Data is read by the host from the Receiver Buffer (RX Buffer). The RX Buffer corresponds to
the Receiver Buffer Register in a 16550A device. In FIFO mode, the RX FIFO operates transparently
behind the RX Buffer. Interface operation is described with reference to the RX Buffer in FIFO and non-
FIFO modes.
Transmit Data
Transmit Data is loaded by the host into the Transmit Buffer (TX Buffer). The TX Buffer corresponds to
the Transmit Holding Register in a 16550A device. In FIFO mode, the TX FIFO operates transparently
behind the TX Buffer. Interface operation is described with reference to the TX Buffer in both FIFO and
non-FIFO modes.
Receiver FIFO Interrupt Operation
Receiver Data Available Interrupt
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (RX Data Available) is enabled
(IER0 = 1), receiver interrupt operation is as follows:
1. The Receiver Data Available Flag (LSR0) is set as soon as a received data character is
available in the RX FIFO. LSR0 is cleared when RX FIFO is empty.
2. The Receiver Data Available Interrupt code (IIR0-IIR4 = 4h) is set whenever the number of
received data bytes in the RX FIFO reaches the trigger level specified by FCR6-FCR7 bits. It is
cleared whenever the number of received data bytes in the RX FIFO drops below the trigger
level specified by FCR6-FCR7 bits.
3. The HINT interrupt is asserted whenever the number of received data bytes in the RX FIFO
reaches the trigger level specified by FCR6-FCR7 bits. HINT interrupt is de-asserted when the
number of received data bytes in the RX FIFO drops below the trigger level specified by FCR6-
FCR7 bits.
Receiver Character Timeout Interrupts
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (Receiver Data Available) is
enabled (IER0 = 1), receiver character timeout interrupt operation is as follows:
1. A Receiver character timeout interrupt code (IIR0-IIR3 = Ch) is set if at least one received
character is in the RX FIFO, the most recent received serial character was longer than four
continuous character times ago (if 2 stop bits are specified, the second stop bit is included in
this time period), and the most recent host read of the RX FIFO was longer than four
continuous character times ago.
Transmitter FIFO Interrupt Operation
Transmitter Empty Interrupt
When the FIFO mode is enabled (FCR0 = 1) and transmitter interrupt (TX Buffer Empty) is enabled
(IER0 =1), transmitter interrupt operation is as follows:
1. The TX Buffer Empty interrupt code (IIR0-IIR3 = 2h) will occur when the TX Buffer is empty. It
is cleared when the TX Buffer is written to (1 to 16 characters) or the IIR is read.
2. The TX Buffer Empty indications will be delayed 1 character time minus the last stop bit time
whenever the following occur: THRE = 1 and there have not been at least two bytes at the
same time in the TX FIFO Buffer since the last setting of THRE was set. The first transmitter
interrupt after setting FCR0 will be immediate.