User guide

CommPlete Series 4000 Server SBC, Model IPC-623C 61
Award BIOS Setup
EDO CASx# MA Wait State
You can select the timing control type of EDO DRAM CAS MA
(memory address bus).
EDO RASx# Wait State
You can select the timing control type of EDO DRAM RAS MA
(memory address bus).
SDRAM RAS-to-CAS Delay
You can select RAS to CAS Delay time in HCLKs of 2/2 or 3/3.
The system board designer should set the values in this field,
depending on the DRAM installed. Do not change the values in
this field unless you change specification of the installed DRAM
or the installed CPU.
SDRAM RAS Precharge Time
Defines the length of time the Row Address Strobe is allowed to
precharge.
SDRAM CAS Latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The
system board designer should set the values in this field,
depending on the DRAM installed. Do not change the values in
this field unless you change specification of the installed DRAM
or the installed CPU.
SDRAM Precharged Control
When enabled, all CPU cycles to SDRAM result in an All Banks
Precharged Command on the SDRAM interface.
DRAM Data Integrity Mode
Select parity or ECC (error-correcting code) according to the
type of install DRAM.
System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance.
However, if any program writes to this memory area, a system
error may result.