User guide

CommPlete Series 4000 Server SBC, Model IPC-551 57
Award BIOS Setup
Auto Configuration Function:
When this option is Enabled, the BIOS automatically configures cache
and clock settings based on detection of the CPU clock speed. The
user cannot change the other parameters. Set this option to
Disabled to do manual setting of DRAM , cache, and I/O bus
clock operating parameters. Enabled is default.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully
chosen and should only be altered if data is being lost. One data-loss
scenario that relates to DRAM timing values occurs when the
computer contains mixed-speed DRAM chips; greater delays may be
required to preserve the integrity of the data held in the slower
memory chips and, consequently, data may be lost.
ISA Clock:
Defines the clock value for the ISA bus. Usually, the ISA bus clock
should be programmed to 8Mhz. For example, when the PCI clock is
33MHz, choose PCICLK/4. PCICLK/4 is the default value.
Cache Features
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at F0000H-
FFFFFH are cached.
Enabled BIOS access cached
Disabled BIOS access not cached
Disabled is the default.