User guide

56 CommPlete Series 4000 Server SBC, Model IPC-551
Award BIOS Setup
5-5 Chipset Features Setup
This menu lets you configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. However, these parameters should never
need to be altered. The default settings have been chosen because
they provide the best operating conditions for your system. The only
time you might consider making any changes would be if you
discovered that data was being lost while using your system.
If you choose CHIPSET FEATURES SETUP from the CMOS
Setup Utilities menu, the following screen appears.
Esc: Quit
F1: Help
F5: Old Values
F6: Load BIOS Defaults
F7: Load Setup Defaults
Pu/Pd/+/-: Modify
(Shift) F2: Color
:SELECT ITEM
ROM / PCI / ISA BIOS (2A59FP6C)
BIOS FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration :Enable
DRAM Timing : 70 ns
DRAM RAS# Precharge Time :4
DRAM R/W Leadoff Timing :7/6
Fast RAS# to CAS# Delay :3
DRAM Read BUrst (EDO/FPM) :x333/x444
DRAM Write Burst Timing :x333
Turbo Read Leadoff :Disabled
DRAM Speculative Leadoff :Disabled
Turn-Around Insertion :Disabled
ISA Clock :PCICLK/4
System BIOS Cacheable :Disabled
Video BIOS Cacheable :Disabled
8-Bit I/O Recovery Time :1
16-Bit I/O Recovery Time :1
Memory Hole at 15M-16M :Disabled
Peer Concurrency :Enabled
Chipset Special Features :Enabled
DRAM ECC/Parity Select :Parity
Memory Parity / ECC Check :Auto
Single Bit Error Report :Enabled
L2 Cache Cacheable Size :64MB
Chipset NA# Asserted :Enabled
Pipeline Cache Timing :Faster
Passive Release :Enabled
Delayed Transaction :Disabled
Figure 5-6: Chipset Features Setup
By moving cursor to the desired field and pressing < F1 > key, all
values for that field will be displayed.