Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
CCD BIAS VOLTAGES
CCD bias voltages (VRD, VOG, VLG) are supplied by filtered outputs of adjustable potentiometers. Fixed CCD bias voltages
(LOD, VSS, GUARD) are supplied by filtered outputs of voltage dividers.
CCD IMAGE SENSOR
This evaluation board supports the following Kodak Full Frame (KAF) CCD image sensors:
KAF-0261E, KAF-0402E, KAF-0402ME, KAF-0401LE, KAF-1001E, KAF-1301E, KAF-1301LE, KAF-1402E, KAF-1402ME, KAF-
1602E, KAF-1602LE, KAF-3200E, KAF-3200ME, KAF-4202, KAF-6303E, KAF-6302LE, KAF-16801E, KAF-16801LE, KAF-
4301E
A/D CONVERTER: ANALOG DEVICES AD9816
The AD9816 is a 12 bit, 6 MSPS CCD analog signal processor. The IC provides an integrated correlated double sampling
(CDS), 8 bit programmable gain, and 8 bit DC offset adjust. Timing signals are provided by PLD1. Default register values
are downloaded from PLD2 upon power up. Alternate programming of its registers can be achieved via external serial
interface or by manually setting the address and data switches on the board and pressing the capture button.
EMITTER FOLLOWER
The video out of the CCD is buffered using a bipolar junction transistor in the emitter follower configuration.
AC COUPLING CAPACITOR
A 1200pF input coupling capacitor removes the DC component of the video signal.
POWER ON CLEAR / RESET
Resets and initializes the board on power up or when the Reset button in pressed.
JTAG HEADER
A 10-pin header provides the user with the ability to reprogram the Altera 7000S PLDs in system via Altera’s ByteBlaster
programming hardware.
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p8