Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX

TABLE OF TABLES
Table 1: Board Inputs, Outputs, Switches....................................................................................................................................22
Table 2: CCD Modes......................................................................................................................................................................23
Table 3: Binning Modes ................................................................................................................................................................23
Table 4: Binning Modes when Configured for use with the KAF-16801E/LE ............................................................................24
Table 5: KAF-4301E SW2 Pixel Rate Settings..............................................................................................................................24
Table 6: Integration Time Modes..................................................................................................................................................25
TABLE OF FIGURES
Figure 1: System Block Diagram .................................................................................................................................................19
Figure 2: Clocking State Machine ................................................................................................................................................20
Figure 3: AD9816 Register Configuration ....................................................................................................................................21
Figure 4: Pixel Rate Timing ..........................................................................................................................................................26
Figure 5: Line Rate Timing for KAF-0261E, 0402E, 1001E, 1301E, 1402E, .................................................................................27
Figure 6: Line Rate Timing for KAF-16801E/LE Sensors............................................................................................................28
Figure 7: Frame rate timing for the KAF-0261E, 0402E, 1001E, 1301E, 1402E,.........................................................................29
Figure 8: Frame Timing for the KAF-3200ME Sensor.................................................................................................................30
Figure 9: Pixel Rate Timing for the KAF-3200ME, KAF-16801E, KAF-16801LE Sensors ..........................................................31
Figure 10: Still Mode: Flush and Integration Timing...................................................................................................................32
Figure 11: Free Run Mode: Integration Timing............................................................................................................................32
Figure 12: Binning Mode Timing (2x2 binning shown).................................................................................................................33
Figure 13: Measured Linearity .....................................................................................................................................................34
Figure 14: Measured Performance: Noise Floor.........................................................................................................................34
Figure 15: Measured Performance: Dynamic Range..................................................................................................................35
Figure 16: Measured Performance: A/D Programmable Gain ...................................................................................................36
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p4










