Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
Linearity of Programmable Analog Gain
0
200
400
600
0 15 30 45 75 90 105 120 150 165 180 195 225 255
Programmable Gain Code
A/D Units
800
60 135 210 240
PGA Gain
0
1
2
3
4
5
6
7
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
Programmable Gain Code
Measured Gain
0.9
0.95
1
1.05
1.1
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
Programmable Gain Code
Incremental Gain
Ideal Delta = 1.019
Measured
Figure 16: Measured Performance: A/D Programmable Gain
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p36