Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
Video
Vpixbinned
Reset
H1
H2
1 count = 8*(bin mode)*t
Clamp
Sample
A/D clock
PIX
1t
1t
8t
3t
t = 1/system clock
(Default Setting =200ns)
4t
3t
Pixel Rate Timing
Figure 12: Binning Mode Timing (2x2 binning shown)
In Binning Modes, the Frequency of the Reset, Clamp, Sample, A/D, and PIX clocks are decreased in order to allow charge
to accumulate on the output node of the CCD before being reset. See Application Note MTD/PS-0900 KAF Series Full-
Frame CCD Series Binning Mode Operation for more details on Full Frame CCD Binning.
V1
V2
Line Rate Timing
Number of pulses = bin mode +1
Number of pulses = bin mode
In Binning Modes, additional lines of charge are summed in the CCD’s horizontal register before being clocked to the
output node.
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p33