Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
Still Mode: Flush and Integration Timing
Line 0
Integration Time
V1
V2
LINE*
PIX*
FRAME*
Line N
CCD Readout Time
Flush Timing
T = 128t
4000 T
IMAGE ACQUIRE
5t
66t**
INTEGRATE
7t
5t
sh and Figure 10: Still Mode: Flu Integration Timing
Free Run Mode: Integration Timing
CCD Readout Time
Line N-1
Line N
Line 0 Line 1
Frame N+1
1 Frame = N Lines
Integration Time
V1
V2
LINE*
PIX*
FRAME*
INTEGRATE
7t
5t
3t
CCD Readout Time
Frame N
1 Frame = N Lines
Figure 11: Free Run Mode: Integration Timing
t = 1/system clock (Default Setting = 200ns)
Note: Default Frame Grabber Settings
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p32