Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
Integration Time
V1
V2
H1
H2
Clamp
Sample
A/D clk
LINE*
R
PIX*
FRAME*
64 t
t = 1/system clock (Default Setting = 200ns)
5t
64 t64 t
2t
50t
12t
140t
25t
222t
Figure 5: Line Rate Timing for KAF-0261E, 0402E, 1001E, 1301E, 1402E,
Note: The line rate timing for the KAF-4301E is similar to this with the addition of an overlap period in the vertical clock
timing. Consult the current specification for the KAF-4301E for details.
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p27