Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
SW7 Swit
(Coarse)
itch
(Coarse)
ration Time
onds)
ch Setting INT 5-3 Sw Integ
(Sec
0 000 0
1 001 1
2 010 2
3 011 3
4 100 4
5 101 5
6 110 7
7 111 9
SW6 Switch Setting INT 2-0 Switch Setting Integration Time
(Fine)
Fine
(ms)
0 000 0*
1 001 20
2 01 50 0
3 100 011
4 100 200
5 101 300
6 110 500
7 11 800 1
Table 6: Integration Time Modes
Note: If both SW7 and SW6 are set to zero, the integration time is set to 10ms.
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p25