Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
Bin Switch (SW2) Setting Binning Mode
1 1x1 (No Binning)
2 1x1 (No Binning)
3 1x1 (No Binning)
4 1x1 (No Binning)
5 1x1 (No Binning)
6 1x1 (No Binning)
7 1x1 (No Binning)
0 1x1 (No Binning)
Tabl en Configured for use with the K 801E/LE
Note: In order to operate the KAF- sensor using the KAF Series CC gital Refer Evaluation Board, the
oard is configured with a unique PLD program. That PLD program does not support binning modes other than 1x1
full resolution readout).
e 4: Binning Modes wh AF-16
16801E/LE D Di ence
b
(normal
KAF-4301E SW2 Setting Pixel rate
0 1.25 MHz
1 .. 7 2.5 MHz
Table 5: KAF-4301E SW2 Pixel Rate Settings
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p24