Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
C Sett /Frame CD Switch ing CCD Pixels/Line Lines
0 Mode1 or KAF-1680 2 * Test 1E/LE 100
1 1E 1500 1200 KAF-140
2 ode 2 4 Test M 10
3 KAF-1301E, KAF-1301LE 1500 1200
4 KAF-4202 2150 2300
5 2E, KAF-1602LE 00 KAF-160 1700 11
6 03E, KAF-6302LE 2150 KAF-63 3300
7 KAF-0401E, KAF-0401LE 1000 650
8 KAF-3200ME 1600 2300
9 -1001E 1150 KAF 1200
A KAF-0261E 700 650
B 16800 4200 KAF- 4300
C KAF-4301E 2300 2200
Tab
Note: In order to operate 6801E/LE sensor u F Series CCD Digital Reference Evaluation Board, the
board is configured with a unique PLD program. This is for the KAF-16801E and KAF-16801LE for that
ase. When the board is configured for the KAF-16801E/LE, this mode will produce 4300 pixels per line and 4200 lines per
frame. For er se st mode as d
in Switch Setting
le 2: CCD Modes
the KAF-1 sing the KA
the switch setting
c
all the oth nsors, this is a te escribed in the table.
B Binning Mode
1 1x1 (No Binning)
2 2x2
3 3x3
4 4x4
5 5x5
6 6x6
7 8x8
0 10x10
Table 3: Binning Modes
Note: Binning Mode is not included in the timing program for the KAF-16801E, KAF-16801LE and KAF-4301E image
sensors.
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p23