Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
Switches witches Select wh ol of modes comeLine/S ere contr s from
Switch_Int[5..0] Integration timing control lines
Switch_Bin[2..0] Binning mo control lines de
Switch_CCD[3..0] Device Select (KAF 0400, KAF1600 ... )
un Selects mode of operation Still/Free-R
/ex Select how ing is controlled A/D_in A/D programm
Sync_test_pix/line Select fram to be perform d e grabber diagnostic e
Sync_test_enable Enable/Dis sync test able frame grabber
Inputs lk 8X Pixel aximum) System_c clock (48 MHz m
tegrate_clk Unit Integrain tion Time clock
Image_Acquire Still mode image acquisition command line, O
Capture butto
R,
n input
5..0] rationInt[ Integ timing control lines
n[2..0] ing mo s Bi Binn de control line
rial Clock A/D useSe For
rial Data or A/D useSe F
ial Load A/D useSer For
Header pin headJTAG 10- er for ISP
12 Bits Di l TTL Digital information Outputs Dout[11..0](+/-) fferentia
FRAME (+/-) Differential grabber frame sync sig TTL frame nal
LINE (+/-) Differential grabber line sync signa TTL frame l
PIX (+/-) Differential ixel sync sign TTL frame grabber p al
INTEGRATE Active high in integratio an be used to
sync LED’s tate.
signal indicates when n state. C
or shutter with this s
Table 1: Board Inputs, Outputs, Switches
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p22