Specifications

Address Register Function Default
Programming
0 Configuration Register
bit 7 MSB test mode bit always 0 0
bit 6 test mode bit always 0 0
bit 5 CDS mode bit High for CDS
Low for SHA mode
1
bit 4 input span High for 3V 1
bit 3 input span High for 1.5V 0
bit 2 channel mode High for 3 channel 0
bit 1 channel mode High for I channel 1
bit 0 test mode bit Always 0 0
1 MUX Register
bit 7 test mode bit always 0 0
bit 6 channel sequence High for BGR 0
bit 5 channel sequence High for RGB 0
bit 4 channel select High for Red 0
bit 3 channel select High for Green 1
bit 2 channel select High for Blue 0
bit 1 test mode bit always 0 0
bit 0 test mode bit always 1 1
2 Red PGA Register 1X to 6X* 0 (1X)
3 Green PGA Register 1X to 6X* 0 (1X)
4 Blue PGA Register 1X to 6X* 0 (1X)
5 Red Offset Register -100mv to 100mv** 0 (0mV)
6 Green Offset Register -100mv to 100mv** 0 (0mV)
7 Blue Offset Register -100mv to 100mv** 0 (0mV)
Note: PGA Gain = 1+(gain code/ 51.2) ** 01111111 = +100mV, 00000000 = 0 mV, 11111111 = -100mV
Figure 3: AD9816 Register Configuration
SLOAD
SDATA
SCLK
D7 D0A2 A0R/W*
* R/W Low for Write, High for Read
3 Wire Serial Interface Timing
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p21