Specifications

FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
Figure 1: System Block Diagram
Guard
VOG
VSS, VLG
VSUB
1200 pF
CDSCLK1
CDSCLK2
ADCCLK
12 Bits AD9816
1K
10uF
+5V
Unit Integration Time
Power_on_clear
Altera
7000S
PLD 2
40 Mhz
Clock
J6
34 pos
SCLK
SDATA
SLOAD
(LED/Shutter Sync)
J4 (40 pos Connecter)
VCC
A/D_in/ex
4 X
Diff
TTL
Line
Drivers
8 bit
s
Line
Driver
10 pin JTAG
Header
Pixclk
Frame
Line
Still/Free-
Run
Int[5..0]
Bin[2..0]
Capture Button
Video in
J8
24 position connector J2
R
C
2X
Octal
Latch
8 bit
Line
Drivers
Line/Switches
Switch_CCD[3..0]SW1
SW2
Switch_Bin[2..0]
SW3
Switch_Int[5..0]
+15V
-10V
LT1372
Switching
+5V
J5
Supply
7414
+18V
-18V
VCC
VCC
Altera
7000S
PLD 1
SW4
Emitter
Follower
Vclks Driver
VRD
J1 24 position connector
VDD
Hclks Driver
Rclk Driver
CCD
Sensor
CCD Daughter Board
J7
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p19