Specifications
Table Of Contents
- INTRODUCTION
- OVERVIEW
- SPECIFICATIONS
- ARCHITECTURE OVERVIEW
- MASTER CLOCK
- PLD1
- PLD2
- CCD CLOCK DRIVERS
- CCD BIAS VOLTAGES
- CCD IMAGE SENSOR
- A/D CONVERTER: ANALOG DEVICES AD9816
- EMITTER FOLLOWER
- AC COUPLING CAPACITOR
- POWER ON CLEAR / RESET
- JTAG HEADER
- UNIT INTEGRATION TIME
- J6 INPUT CONNECTOR
- J4 OUTPUT CONNECTOR
- J7 INTEGRATION SYNC
- J1, J2 IMAGER BOARD CONNECTORS
- POWER SUPPLIES
- J5 POWER CONNECTOR
- BOARD REQUIREMENTS:
- CONFIGURATION MODES
- CCD IMAGER BOARDS
- TIMING
- OTHER PARAMETERS
- FIGURES, TABLES, TIMING DIAGRAMS, AND PERFORMANCE DATA
- REFERENCES
- ORDERING INFORMATION
- WARNING: LIFE SUPPORT APPLICATIONS POLICY
- REVISION CHANGES
- APPENDIX
OUTPUT SELECTION FOR SENSORS WITH TWO OUTPUTS
The KAF-1001E, KAF-0261E, and KAF-4301E sensors have two video outputs. The outputs have different gain and one of
them is selected depending on the application. The imager daughter boards for these sensors have two jumpers that must
be set correctly to enable the desired output.
To select the high gain output, Vout2:
Set J3 to the VID2 position:
et the two jumpers on J4 as follows:
To select the low gain output, Vout1:
Set the two jumpers on J4 as follows:
ote: The schematic for the KAF-1001 imager daughter board contains an error. The library element for the imager
indicates that pin 5 is Vout1 and pin 12 is Vout2. These are incorrect and are reversed in that part of the schematic.
However, the labeling on the imager board is correct. Only the pin labeling on the schematic is incorrect.
VID12
J3
S
J4
Bias
Bias
H22
H2
H21
Set J3 to the VID1 position:
VID12
J3
J4
Bias
Bias
H22
H2
H21
N
©Eastman Kodak Company, 2008 www.kodak.com/go/imagers Revision 8.0 MTD/PS-0215 p17