Specifications

Table Of Contents

CCD IMAGER BOARDS

Each CCD has an imager board. The imager boards route the bias voltage traces from the timing board through

connectors J1 and J2 to the appropriate pins on the device. The imager boards contain the Horizontal and Reset clock

driver ICs as well as the emitter-follower circuit that buffers and drives the video signal down to the timing board.

ADJUSTMENTS

Fixed Bias Voltages:

Fixed Voltages:

VDD +15V

LOD/GUARD +10V

VSUB 0V

VSS 0 to +2.1V*

Note: The VSS bias voltage is set by the inclusion of up to three series diodes on the imager board. Therefore 0V is

achieved by shorting across all three diode positions. This bias is preset at the factory depending on the appropriate CCD

specification.

Variable Bias Voltages:

Variable Voltage:*

Function Adjustment Potentiometer

VOG R12

VRD R11

VLG R13

V_PP (vertical clk peak to peak swing ) R17

VCLK (vertical clk level adjust) R67

H_PP (horizontal clk peak to peak swing ) R64 (imager board)

HCLK (horizontal clk level adjust) R14 (imager board)

R_PP (reset clk peak to peak swing) R18 (imager board)

RCLK (reset clk level adjust) R27 (imager board)

Note: These voltages are optimized for the particular KAF Series image sensor being used and are fixed at the factory

according to the image sensor specification. Adjustments should not be made to them without consulting the ISS.