Specifications

Table Of Contents

ADJUSTMENTS

Adjustments can be made to the A/D registers during operation of the board by utilizing the DATA dipswitch (SW10), the

ADDRESS switch (SW9), and the Image_Acquire control line. After setting SW9 to the desired Address, and SW10 to the

desired Data, send an Image_Acquire signal either by pressing the Image_Acquire button or remotely via the J6 connector

control line. This will load the new value into PLD2 and a state machine inside the PLD will then serial load the new data

into the A/D’s register. This is true whether or not the board is running in Still or Free Run Mode. (See Figure 3: AD9816

CCD MODES

The CCD Select switch (SW1) setting determines the line and frame length timing.

This switch is pre-set at the ISS. (See Table 2: CCD Modes)

BINNING MODES

The BIN Select switch (SW2) setting determines the Binning mode operation. (Table 3: Binning Modes)

INTEGRATION MODES

The INT Select switches (SW6, SW7) settings determine the Integration Time.

SW6 is the Coarse Adjust. SW7 is the Fine Adjust. (Table 6: Integration Time Modes)

FRAME GRABBER DIAGNOSTIC MODES

When set to ENABLE, the Sync_Test_Enable switch (SW12) tri-states the 12-bit output bus out of the A/D converter, and

enables the output of either the pixel number or the line number onto the output bus, depending on how the

Sync_Test_pix/line Jumper is set (SW11). This provides a diagnostic test to make certain the Frame Grabber is

synchronized correctly with the board.

The line counter in PLD1 is a binary up-counter, therefore the line count that is output to the output bus will increment

sequentially (0,1,2,3,4,5.....) until the last line in the frame.

The pixel counter in PLD1 is a gray code up counter, therefore the pixel count that is output to the output bus will

increment in gray code transition counts (0,1,3,2,6,7,5,4......) until the last pixel in the line.