Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
4.3.27 Interrupt Line Register
This read/write register, which the system programs, indicates to the software which interrupt line that the
XIO3130 downstream port has assigned to it. The default value of this register is FFh, which indicates that
an interrupt line has not yet been assigned to the function. This register is essentially a scratch-pad
register; it has no effect on the XIO3130 itself.
PCI register offset: 3Ch
Register type: Read/Write
Default value: FFh
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 1 1 1 1 1 1 1 1
4.3.28 Interrupt Pin Register
The Interrupt Pin register is read-only, which indicates that the XIO3130 downstream ports generate INTx
interrupts as follows:
• Downstream port 0 on PCI Interrupt pin INTA (register value of 01h)
• Downstream port 1 on PCI Interrupt pin INTA (register value of 01h)
• Downstream port 2 on PCI Interrupt pin INTA (register value of 01h)
Interrupts originated by XIO3130 downstream ports are associated with the primary side of the
downstream port PCI-to-PCI bridge, and as a result are only passed through the upstream port PCI-to-PCI
bridge as described in PCI Express Base Specification Revision 1.1, Page 69, Table 2-13.
PCI register offset: 3Dh
Register type: Read only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
4.3.29 Bridge Control Register
The Bridge Control register provides extensions to the Command register that are specific to a bridge.
PCI register offset: 3Eh
Register type: Read/Write; Read Only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-66. Bit Descriptions – Bridge Control Register
BIT FIELD NAME ACCESS DESCRIPTION
15:12 RSVD r Reserved. When read, these bits return zeros.
11 DTSERR r Discard timer SERR enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
10 DTSTATUS r Discard timer status. This bit is hardwired to zero. This bit does not apply to PCI Express.
9 SEC_DT r Secondary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
8 PRI_DEC r Primary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
7 FBB_EN r Fast back-to-back enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
98 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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