Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

www.ti.com

Table 4-61. Bit Descriptions – Pre-fetchable Memory Limit Register

BIT FIELD NAME ACCESS DESCRIPTION

Pre-fetchable memory limit. This field defines the top address of the pre-fetchable memory

address range that is used to determine when to forward memory transactions from one

15:4 PRELIMIT rw interface to the other. These bits correspond to address bits [31:20] in the memory address.

The lower 20 bits are assumed to be FFFFFh. The Pre-fetchable Limit Upper 32 Bits register

is used to specify the bit [63:32] of the 64-bit pre-fetchable memory address.

64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for

3:0 64BIT r

this memory window.

4.3.22 Pre-fetchable Base Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Base register.

PCI register offset: 28h

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-62. Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register

BIT FIELD NAME ACCESS DESCRIPTION

Pre-fetchable memory base upper 32 bits. This field defines the upper 32 bits of the bottom

31:0 PREBASE rw address of the pre-fetchable memory address range that is used to determine when to forward

memory transactions downstream.

4.3.23 Pre-fetchable Limit Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Limit register.

PCI register offset: 2Ch

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-63. Descriptions – Pre-fetchable Limit Upper 32 Bits Register

BIT FIELD NAME ACCESS DESCRIPTION

Pre-fetchable memory limit upper 32 bits. This field defines the upper 32 bits of the top address

31:0 PRELIMIT rw of the pre-fetchable memory address range that is used to determine when to forward memory

transactions downstream.

Submit Documentation Feedback

Product Folder Link(s): XIO3130