Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
4.3.19 Memory Limit Register
This read/write register specifies the upper limit of the memory addresses that the downstream port
forwards downstream.
PCI register offset: 22h
Register type: Read/Write; Read Only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-59. Bit Descriptions – Memory Limit Register
BIT FIELD NAME ACCESS DESCRIPTION
Memory limit. This field defines the top address of the memory address range that is used to
determine when to forward memory transactions from one interface to the other. These bits
15:4 MEMLIMIT rw
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to
be FFFFFh.
3:0 RSVD r Reserved. When read, these bits return zeros.
4.3.20 Pre-fetchable Memory Base Register
This read/write register specifies the lower limit of the pre-fetchable memory addresses that the
downstream port forwards downstream.
PCI register offset: 24h
Register type: Read/Write; Read Only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4-60. Descriptions – Pre-fetchable Memory Base Register
BIT FIELD NAME ACCESS DESCRIPTION
Pre-fetchable memory base. This field defines the bottom address of the pre-fetchable
memory address range that is used to determine when to forward memory transactions from
15:4 PREBASE rw one interface to the other. These bits correspond to address bits [31:20] in the memory
address. The lower 20 bits are assumed to be zero. The Pre-fetchable Base Upper 32 Bits
register is used to specify the bit [63:32] of the 64-bit pre-fetchable memory address.
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for
3:0 64BIT r
this memory window.
4.3.21 Pre-fetchable Memory Limit Register
This read/write register specifies the upper limit of the pre-fetchable memory addresses that the
downstream port forwards downstream.
PCI register offset: 26h
Register type: Read/Write; Read Only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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