Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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Table 4-57. Bit Descriptions – Secondary Status Register
BIT FIELD NAME ACCESS DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP
on the downstream port. This bit is set regardless of the state of the Parity Error Response bit
in the Bridge Control register.
15 PAR_ERR rcu
0 – No parity error detected.
1 – Parity error detected.
Received System Error. This bit is set when the XIO3130 sends an ERR_FATAL or
ERR_NONFATAL message upstream and the SERR Enable bit in the Command register is set.
14 SYS_ERR rcu
0 – No error signaled.
1 – ERR_FATAL or ERR_NONFATAL signaled.
Received master abort. This bit is set when the downstream PCI Express interface of the
XIO3130 receives a completion with Unsupported Request Status.
13 MABORT rcu
0 – Unsupported Request not received.
1 – Unsupported Request received on.
Received target abort. This bit is set when the downstream PCI Express interface of the
XIO3130 receives a completion with Completer Abort Status.
12 TABORT_REC rcu
0 – Completer Abort not received.
1 - Completer Abort received.
Signaled target abort. This bit is set when the downstream PCI Express interface completes a
Request with Completer Abort Status.
11 TABORT_SIG rcu
0 – Completer Abort not signaled.
1 – Completer Abort signaled.
10:9 PCI_SPEED r DEVSEL timing. These bits are hardwired to 00. These bits do not apply to PCI Express.
Master data parity error. This bit is set when the XIO3130 receives a poisoned completion or
8 DATAPAR rcu poisons a write request on the downstream PCI Express interface. This bit is never set if the
parity error response enable bit in the Bridge Control register is clear.
7 FBB_CAP r Fast back-to-back capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
6 RSVD r Reserved. When read, this bit returns zero.
5 66MHZ r 66-MHz capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
4:0 RSVD r Reserved. When read, these bits return zeros.
4.3.18 Memory Base Register
This read/write register specifies the lower limit of the memory addresses that the downstream port
forwards downstream.
PCI register offset: 20h
Register type: Read/Write; Read Only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-58. IBit Descriptions – Memory Base Register
BIT FIELD NAME ACCESS DESCRIPTION
Memory base. This field defines the bottom address of the memory address range that is
used to determine when to forward memory transactions from one interface to the other.
15:4 MEMBASE rw
These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are
assumed to be zero.
3:0 RSVD r Reserved. When read, these bits return zeros.
94 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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