Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
4.3.7 Cache Line Size Register
The Cache Line Size register is implemented by PCI Express devices as a read-write field for legacy
compatibility, but has no impact on any PCI Express device functionality.
PCI register offset: 0Ch
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.3.8 Primary Latency Timer Register
This read-only register has no meaningful context for a PCI Express device, so it returns zeros when read.
PCI register offset: 0Dh
Register type: Read only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.3.9 Header Type Register
This read-only register indicates that this function has a Type 1 PCI header. Bit seven of this register is
zero, indicating that the XIO3130 downstream port PCI-to-PCI bridge is not a multifunction device.
PCI register offset: 0Eh
Register type: Read only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
4.3.10 BIST Register
Since the XIO3130 does not support a built-in self test (BIST), this read-only register returns the value 00h
when read.
PCI register offset: 0Fh
Register type: Read only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 91
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