Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 4-51. Extended Configuration Space (Downstream Port)
Register Name Offset
Next Capability Offset / Capability Version PCI Express Advanced Error Reporting Capabilities ID 100h
Uncorrectable Error Status Register 104h
Uncorrectable Error Mask Register 108h
Uncorrectable Error Severity Register 10Ch
Correctable Error Status Register 110h
Correctable Error Mask 114h
Advanced Error Capabilities and Control 118h
Header Log Register 11Ch
Header Log Register 120h
Header Log Register 124h
Header Log Register 128h
Reserved 12Ch-FFCh
4.3.2 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas
Instruments.
PCI register offset: 00h
Register type: Read only
Default value: 104Ch
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0
4.3.3 Device ID Register
This 16-bit read-only register contains the device ID assigned by TI to the XIO3130. The value in this
register is the same for all downstream ports, as defined in the following table.
PCI register offset: 02h
Register type: Read only
Default value: 8233h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1
4.3.4 Command Register
The Command register controls the way the downstream port bridge behaves on its primary interface; i.e.,
the internal PCI bus between the upstream and downstream ports.
PCI register offset: 04h
Register type: Read/Write; Read Only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
88 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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