Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
4.3 PCI Express Downstream Port Registers
The default reset domain for all downstream port registers is SBRST. Some register fields are placed in a
different reset domain from the default reset domain; all bit and field descriptions identify any unique reset
domains. Generally, all sticky bits are placed in the GRST domain and all (non-sticky) EEPROM loadable
bits are placed in the PERST domain.
4.3.1 PCI Configuration Space (Downstream Port) Register Map
Table 4-50. PCI Express Downstream Port Configuration Register Map (Type 1)
Register Name Offset
Device ID Vendor ID 000h
Status Command 004h
Class Code Revision ID 008h
BIST Header Type Latency Timer Cache Line Size 00Ch
Reserved 010h-014h
Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 018h
Secondary Status I/O Limit I/O Base 01Ch
Memory Limit Memory Base 020h
Pre-fetchable Memory Limit Pre-fetchable Memory Base 024h
Pre-fetchable Base Upper 32 Bits 028h
Pre-fetchable Limit Upper 32 Bits 02Ch
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits 030h
Reserved Capabilities Pointer 034h
Reserved 038h
Bridge Control Interrupt Pin Interrupt Line 03Ch
Reserved 040h-04Ch
Power Management Capabilities Next-item Pointer PM CAP ID 050h
PM Data (RSVD) PMCSR_BSE Power Management CSR 054h
Reserved 058h-06Ch
MSI Message Control Next-item Pointer MSI CAP ID 070h
MSI Message Address 074h
MSI Upper Message Address 078h
Reserved MSI Message Data 07Ch
Reserved Next-item Pointer SSID/SSVID CAP ID 080h
Subsystem ID Subsystem Vendor ID 084h
Reserved 088h-08Ch
PCI Express Capabilities Register Next-item Pointer PCI Express Capability ID 090h
Device Capabilities 094h
Device Status Device Control 098h
Link Capabilities 09Ch
Link Status Link Control 0A0h
Slot Capabilities A4h
Slot Status Slot Control A8h
Reserved 0ACh-0C4h
TI Proprietary 0C8h-0D0h
General Control 0D4h
Reserved 0D8h-0E8h
General Slot Info Reserved LOs Idle Timeout 0ECh
Reserved 0F0h-0FCh
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