Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-46. Uncorrectable Error Severity Register
BIT FIELD NAME ACCESS DESCRIPTION
31:21 RSVD r Reserved. Return zeros when read.
Unsupported Request error severity.
20 UR_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Extended CRC error severity.
19 ECRC_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Malformed TLP severity.
18 MAL_TLP_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Receiver Overflow severity.
17 RX_OVERFLOW_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Unexpected Completion severity.
16 UNXP_CPL_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completer Abort severity.
15 CPL_ABORT_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completion Timeout severity.
14 CPL_TIMEOUT_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Flow Control error severity.
13 FC_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Poisoned TLP severity.
12 PSN_TLP_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
11:6 RSVD r Reserved. Return zeros when read.
Surprise Down error severity.
5 SD_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Data Link Protocol error severity.
4 DLL_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
3:1 RSVD r Reserved. Return zeros when read.
0 Undefined r The value read from this bit is undefined.
4.2.81 Correctable Error Status Register
The Correctable Error Status register reports the status of individual errors as they occur. Software may
clear these bits only by writing a 1 to the desired location.
PCI register offset: 110h
Register type: Read Only, Cleared by a Write of one
Default value: 0000 0000h
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Product Folder Link(s): XIO3130