Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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Table 4-45. Uncorrectable Error Mask Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Malformed TLP mask.
18 MAL_TLP_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Receiver Overflow mask.
17 RX_OVERFLOW_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Unexpected Completion mask.
16 UNXP_CPL_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Completer Abort mask.
15 CPL_ABORT_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Completion Timeout mask.
14 CPL_TIMEOUT_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Flow Control error mask.
13 FC_ERROR_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Poisoned TLP mask.
12 PSN_TLP_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
11:6 RSVD r Reserved. Return zeros when read.
Surprise Down error mask.
5 SD_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Data Link Protocol error mask.
4 DLL_ERROR_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
3:1 RSVD r Reserved. Return zeros when read.
0 Undefined r The value read from this bit is undefined.
4.2.80 Uncorrectable Error Severity Register
The Uncorrectable Error Severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
clear, the corresponding error condition is identified as nonfatal.
PCI register offset: 10Ch
Register type: Read Only, Read/Write
Default value: 0003 2030h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0
82 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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