Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-44. Uncorrectable Error Status Register
BIT FIELD NAME ACCESS DESCRIPTION
31:21 RSVD r Reserved. Return zeros when read.
Unsupported Request error. This bit is asserted when an Unsupported Request error is
20 UR_ERROR rcuh detected (i.e., when a request is received that results in the sending of a completion with
an Unsupported Request status).
19 ECRC_ERROR rcuh Extended CRC error. This bit is asserted when an Extended CRC error is detected.
18 MAL_TLP rcuh Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver overflow. This bit is asserted when the flow control logic detects that the
17 RX_OVERFLOW rcuh
transmitting device has illegally exceeded the number of credits that were issued.
Unexpected completion. This bit is asserted when a completion packet is received that
16 UNXP_CPL rcuh
does not correspond to an issued request.
Completer abort. This bit is asserted when the completion to a pending request arrives with
15 CPL_ABORT rcuh
Completer Abort status.
Completion timeout. This bit is asserted when no completion has been received for an
14 CPL_TIMEOUT rcuh
issued request before the timeout period.
Flow control error. This bit is asserted when a flow control protocol error is detected either
13 FC_ERROR rcuh
during initialization or during normal operation.
Poisoned TLP. This bit is asserted when an outgoing packet (request or completion) has
12 PSN_TLP rcuh been poisoned by setting the poison bit and has inverted the extended CRC attached to
the end of the packet.
11:6 RSVD r Reserved. Return zeros when read.
5 SD_ERROR rcuh Surprise down error. See Surprise Down ECN for a description of this error condition.
4 DLL_ERROR rcuh Data link protocol error. This bit is asserted if a data link layer protocol error is detected.
3:1 RSVD r Reserved. Return zeros when read.
0 Undefined r The value read from this bit is undefined.
4.2.79 Uncorrectable Error Mask Register
The Uncorrectable Error Mask register controls the reporting of individual errors as they occur. When a bit
is set to one, the error status bits are still affected, but the error is not logged and no error reporting
message is sent upstream.
PCI register offset: 108h
Register type: Read Only, Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-45. Uncorrectable Error Mask Register
BIT FIELD NAME ACCESS DESCRIPTION
31:21 RSVD r Reserved. Return zeros when read.
Unsupported Request error mask.
20 UR_ERROR_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
Extended CRC error mask.
19 ECRC_ERROR_MASK rwh 0 - Error condition is unmasked.
1 - Error condition is masked.
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