Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 4-43. Bit Descriptions – Global Switch Control Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Beacon detect disable. This bit disables beacon detection on all downstream ports and allows the
reference macro to be placed in low power state during D3cold.
0 – Beacon detection enabled
0 BCN_DET_DIS rwh
1 – Beacon detection disabled
This field is loaded from EEPROM (when present) and reset with GRST.
4.2.76 Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express Advanced Error
Reporting Capabilities. The register returns 0001h when read.
PCI register offset: 100h
Register type: Read only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
4.2.77 Next Capability Offset/Capability Version Register
This read-only register returns the value 0000h to indicate that this extended capability block represents
the end of the linked list of extended capability structures. The least significant four bits identify the
revision of the current capability block as 1h.
PCI register offset: 102h
Register type: Read only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.2.78 Uncorrectable Error Status Register
This register reports the status of individual errors as they occur. Software may clear these bits only by
writing a 1 to the desired location.
PCI register offset: 104h
Register type: Read Only, Cleared by a Write of one
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
80 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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