Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
List of Tables
2-1 XIO3130 Terminal Assignments................................................................................................ 14
2-2 XIO3130 Terminals Sorted Alphanumerically ................................................................................ 15
2-3 XIO3130 Signal Names Sorted Alphabetically ............................................................................... 16
2-4 Power Supply Terminals ........................................................................................................ 17
2-5 Combined Power Terminals .................................................................................................... 17
2-6 Ground Terminals ................................................................................................................ 18
2-7 PCI Express Reference Clock Terminals ..................................................................................... 18
2-8 PCI Express Terminals .......................................................................................................... 19
2-9 PCI Hot Plug Strapping Terminals ............................................................................................. 19
2-10 GPIO Terminals .................................................................................................................. 20
2-11 Miscellaneous Terminals ........................................................................................................ 21
3-1 Initial Flow Control Credit Advertisements .................................................................................... 24
3-2 Messages Supported by the XIO3130......................................................................................... 25
3-3 EEPROM Register Loading Map............................................................................................... 29
3-4 Register for Programming Serial-Bus Devices ............................................................................... 31
3-5 Switch Reset Options............................................................................................................ 32
4-1 PCI Express Upstream Port Configuration Register Map (Type 1)........................................................ 35
4-2 Extended Configuration Space (Upstream Port) ............................................................................. 36
4-3 Bit Descriptions – Command Register ........................................................................................ 37
4-4 Bit Descriptions – Status Register ............................................................................................. 38
4-5 Bit Descriptions – Class Code and Revision ID Register .................................................................. 39
4-6 Bit Descriptions – I/O Base Register .......................................................................................... 41
4-7 Bit Descriptions – I/O Limit Register .......................................................................................... 42
4-8 Bit Descriptions – Secondary Status Register ............................................................................... 42
4-9 Bit Descriptions – Memory Base Register .................................................................................... 43
4-10 Bit Descriptions – Memory Limit Register .................................................................................... 43
4-11 Bit Descriptions – Pre-fetchable Memory Base Register ................................................................... 44
4-12 Bit Descriptions – Pre-fetchable Memory Limit Register ................................................................... 44
4-13 Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register ............................................................ 44
4-14 Bit Descriptions – Pre-fetchable Limit Upper 32 Bits Register ............................................................ 45
4-15 Bit Descriptions – I/O Base Upper 16 Bits Register ........................................................................ 45
4-16 Bit Descriptions – I/O Limit Upper 16 Bits Register ......................................................................... 45
4-17 Bit Descriptions – Bridge Control Register ................................................................................... 47
4-18 Bit Descriptions – Power Management Capabilities Register ............................................................. 48
4-19 Bit Descriptions – Power Management Control/Status Register .......................................................... 49
4-20 Bit Descriptions – PM Bridge Support Extension Register ................................................................. 50
4-21 Bit Descriptions – MSI Message Control Register .......................................................................... 51
4-22 Bit Descriptions – MSI Message Address Register ......................................................................... 52
4-23 Bit Descriptions – MSI Data Register ......................................................................................... 52
4-24 Bit Descriptions – PCI Express Capabilities Register ...................................................................... 54
4-25 Bit Descriptions – Device Capabilities Register ............................................................................. 55
4-26 Bit Descriptions – Device Control Register .................................................................................. 55
4-27 Bit Descriptions – Device Status Register .................................................................................... 57
4-28 Bit Descriptions – Link Capabilities Register ................................................................................. 57
4-29 Bit Descriptions – Link Control Register ...................................................................................... 58
4-30 Bit Descriptions – Link Status Register ....................................................................................... 59
8 List of Tables Copyright © 2007–2010, Texas Instruments Incorporated