Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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4.2.74 Downstream Ports Link PM Latency Register
This read/write register is used to program L0s and L1 exit latencies for all XIO3130 downstream ports.
Similar information is provided in a separate register for the upstream port.
PCI register offset: E8h
Register type: Read/Write; Read Only
Default value: 3F24h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register
BIT FIELD NAME ACCESS DESCRIPTION
15:14 RSVD r Reserved. When read, these bits return zeros.
Endpoint L0s acceptable latency. This field is used to program the maximum acceptable
latency when exiting the L0s state. This field is used to set the L0s Acceptable Latency field
in the Device Capabilities register.
000 – Less than 64 ns
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
13:11 EP_L0S_LAT rw
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 ms
101 – 1 ms up to less than 2 ms
110 – 2 ms to 4 ms
111 – More than 4 ms (default)
This field is loaded from EEPROM (when present) and reset with PERST.
Endpoint L1 acceptable latency. This field is used to program the maximum acceptable
latency when exiting the L1 state. This field is used to set the L1 Acceptable Latency field in
the Device Capabilities register.
000 – Less than 1 ms
001 – 1 ms up to less than 2 ms
010 – 2 ms up to less than 4 ms
10:8 EP_L1_LAT rw
011 – 4 ms up to less than 8 ms
100 – 8 ms up to less than 16 ms
101 – 16 ms up to less than 32 ms
110 – 32 ms to 64 ms
111 – More than 64 ms (default)
This field is loaded from EEPROM (when present) and reset with PERST.
7:6 RSVD r Reserved. When read, these bits return zeros.
L0s exit latency. This field is used to program the maximum latency for the PHY to exit the
L0s state. This is used to set the L0s Exit Latency field in the Link Capabilities register.
000 – Less than 64 ns
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
5:3 L0S_EXIT_LAT rw
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 ms (default)
101 – 1 ms up to less than 2 ms
110 – 2 ms to 4 ms
111 – More than 4 ms
78 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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