Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
www.ti.com
4.2.65 GPIO Data Register
This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in
output mode. Reads to this register return the state of the GPIO pins, regardless of PCI Hot Plug
strapping or GPIO configuration. Writes to this register only affect pins that are configured as a general
purpose output.
PCI register offset: C4h
Register type: Read/Write; Read Only
Default value: 00000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-39. Bit Descriptions – GPIO Data Register
BIT FIELD NAME ACCESS DESCRIPTION
31:19 RSVD r
GPIO 18 data.
HP_INTX / PD_CHG / GPIO 18 data.
HP_INTX output mode:
Reads indicate current state of pin
Writes have no affect
PD_CHG output mode:
Reads indicate current state of pin
18 PCIE_GPIO18_DATA rw
Writes have no affect
PD_CHG is asserted whenever all of the following are true for any given slot:
PDC[n] bit is asserted in the Slot Status register for switch downstream port n, and
PDC_EN[n] bit is asserted in Slot Control Register for switch downstream port n
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
PWR_OVER / GPIO 17 data.
PWR_OVER mode: reads state of pin; writes have no affect
PWR_OVER pin is asserted whenever any of the following conditions are true:
PERST is asserted
17 PCIE_GPIO17_DATA rw
Conditions are met for exceeding slot power limit (see PWR_OVRD field in
Global Chip Control Register)
GP Input mode: reads state of pin; writes have no affect
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
GP Input mode: reads state of pin; writes have no affect
16 PCIE_GPIO16_DATA rw GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 15 data.
GP Input mode: reads state of pin; writes have no affect
15 PCIE_GPIO15_DATA rw
GP Output mode: reads and also controls state of pin
This field is loaded from EEPROM (if present), and reset with FRST.
72 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): XIO3130