Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-38. Bit Descriptions – GPIO D Control Register
BIT FIELD NAME ACCESS DESCRIPTION
15:10 RSVD r Reserved. When read, these bits return zeros.
GPIO 18 Control. This field controls the GPIO18 pin as follows:
00 – General Purpose Input (default)
01 – General Purpose Output
9:8 PCIE_GPIO18_CTL rw
10 – HP_INTX, PCI Hot Plug Interrupt Output
11 – PD_CHG, Presence Detect Changed Output
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
GPIO 17 Control. This field controls the GPIO19 pin as follows:
00 – General Purpose Input (default)
01 – General Purpose Output
7:6 PCIE_GPIO17_CTL rw
10 – General Purpose Input
11 – PWR_OVER, Power Limits exceeded
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
GPIO 16 Control. This field controls the GPIO16 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ATN_LED0
011 – Port 2 ATN_LED1
5:3 PCIE_GPIO16_CTL rw
100 – Port 3 ATN_LED2
101 – Port 1 PWRFLT0
110 – Port 2 PWRFLT1
111 – Port 3 PWRFLT2
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
GPIO 15 Control. This field controls the GPIO15 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ATN_LED0
011 – Port 2 ATN_LED1
2:0 PCIE_GPIO15_CTL rw
100 – Port 3 PWR_LED2
101 – Port 1 PWRFLT0
110 – Port 2 PWRFLT1
111 – Port 3 PWRFLT2.
See GPIO Data register for a detailed description of this field. This field is loaded from
EEPROM (if present), and reset with FRST.
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 71
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