Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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Table 4-35. Bit Descriptions – GPIO A Control Register (continued)

BIT FIELD NAME ACCESS DESCRIPTION

GPIO 1 Control. This field controls the GPIO1 pin as follows:

000 – General Purpose Input (default)

001 – General Purpose Output

010 – Port 2 EMIL_CTL1

011 – Port 3 EMIL_CTL2

100 – Port 2 ATN_LED1

101 – Port 3 ATN_LED2

5:3 PCIE_GPIO1_CTL rw

110 – Port 2 PWR_LED1

111 – Port 3 PWR_LED2

See GPIO Data register for a detailed description of this field.

This field is loaded from EEPROM (if present), and reset with FRST.

If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO1 terminal

is directly mapped as the PWR_ON PCI Hot Plug terminal for port 2 and is no longer

available for use as a GPIO. In this situation these bits have no meaning and should be left

at their default value.

GPIO 0 Control. This field controls the GPIO0 pin as follows:

000 – General Purpose Input (default)

001 – General Purpose Output

010 – Port 2 ACT_BTN1

011 – Port 3 ACT_BTN2

100 – Port 2 PWRFLT1

101 – Port 3 PWRFLT2

2:0 PCIE_GPIO0_CTL rw

110 – Port 2 EMIL_ENG1

111 – Port 3 EMIL_ENG2

See GPIO Data register for a detailed description of this field.

This field is loaded from EEPROM (if present), and reset with FRST.

If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO1 terminal

is directly mapped as the PWR_ON PCI Hot Plug terminal for port 2 and is no longer

available for use as a GPIO. In this situation these bits have no meaning and should be left

at their default value.

4.2.62 GPIO B Control Register

This register is used to control the function of the PCIE_GPIO 5 – 9 pins.

PCI register offset: BEh

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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