Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-35. Bit Descriptions – GPIO A Control Register
BIT FIELD NAME ACCESS DESCRIPTION
15 RSVD r Reserved. Reads back zero.
GPIO 4 Control. This field controls the GPIO4 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 3 ACT_BTN2
100 – Port 1 PWRFLT0
101 – Port 3 PWRFLT2
14:12 PCIE_GPIO4_CTL rw
110 – Port 1 EMIL_ENG0
111 – Port 3 EMIL_ENG2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO4 terminal
is directly mapped as the PRESENT PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 3 Control. This field controls the GPIO3 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 CLKREQ0
011 – Port 1 MRLS_DET0
100 – Port 2 PWRFLT1
11:9 PCIE_GPIO3_CTL rw
101 – Port 3 PWRFLT2
110 – Port 2 MRLS_DET1
111 – Port 3 MRLS_DET2,
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 2 Control. This field controls the GPIO2 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 2 ACT_BTN1
011 – Port 3 ACT_BTN2
100 – Port 2 PWRFLT1
101 – Port 3 PWRFLT2
8:6 PCIE_GPIO2_CTL rw
110 – Port 2 MRLS_DET1
111 – Port 3 MRLS_DET2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO2 terminal
is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 2 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 65
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