Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
L1 exit latency. This field is used to program the maximum latency for the PHY to exit the L1
state. This field is used to set the L1 Exit Latency field in the Link Capabilities register.
000 – Less than 1 ms
001 – 1 ms up to less than 2 ms
010 – 2 ms up to less than 4 ms
011 – 4 ms up to less than 8 ms
100 – 8 ms up to less than 16 ms (default)
101 – 16 ms up to less than 32 ms
2:0 L1_EXIT_LAT rw
110 – 32 ms to 64 ms
111 – More than 64 ms
Define writtenBySW to default to false, be set to true when the software or serial EEPROM
writes this field to a value that is different from its current state, and can only be subsequently
set to false as a result of a reset. When writtenBySW is false, this field is set to 100b. When
writtenBySW is true, this field is the value last written by the software.
This field is loaded from EEPROM (when present) and reset with PERST.
This field may be programmed differently depending on the values programmed in the
DEFER_L_EXIT and SMART_L_EXIT fields in the Global Switch Control register.
4.2.60 Global Chip Control Register
This read/write register is used to control various functionalities across the entire device.
PCI register offset: B8h
Register type: Read/Write; Read Only; Hardware Update; Sticky
Default value: 0000 000Xh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
Table 4-34. Bit Descriptions – Global Chip Control Register
BIT FIELD NAME ACCESS DESCRIPTION
31 RSVD r Reserved. When read, this bit returns zero.
ASPM-based L1 PLL disable. This bit enables or disables PLL during ASPM-based L1 for
all PHYs on the XIO3130. This setting does not affect D-state-based L1, for which PLLs
must be shut off during L1.
30 ASPM_L1_PLL_DIS rw
0 – Enable PLL during ASPM-based L1.
1 – Disable PLL during ASPM-based L1.
This field is loaded from EEPROM (when present) and reset with PERST.
ASPM-based L1 enable. This bit enables ASPM-based L1 on the PCI Express chip-level
upstream port. This field controls whether the ASPM Support field in the Link Capabilities
register reports support for ASPM-based L1 for all functions in a multifunction device.
29 ASPM_L1_EN rw
0 – Disable ASPM based L1.
1 – Enable ASPM based L1.
This field is loaded from EEPROM (when present) and reset with PERST.
This bit is a reserved diagnostic bit and must be set to 0 for proper operation. If an
28 RSVD rw
EEPROM is used, the corresponding bit in the EEPROM must be set to 0.
27:22 RSVD r Reserved. When read, these bits return zeros.
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 63
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