Specifications

XIO3130

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SLLS693F–MAY 2007–REVISED JANUARY 2010

Table 4-32. Bit Descriptions – Serial Bus Control and Status Register (continued)

BIT FIELD NAME ACCESS DESCRIPTION

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the XIO3130

device is downloading register defaults from a serial EEPROM.

0 – No EEPROM activity

4 ROMBUSY ru

1 – EEPROM download in progress

This field is reset with PERST.

Serial EEPROM detected. This bit is automatically set when a serial EEPROM is detected via

the strapping option. For more information on strapping options, see section 1.9.1. The value

of this bit is used to enable the serial bus interface and to control whether the EEPROM load

occurs. Note that a serial EEPROM is only detected once following PERST or GRST.

0 – No EEPROM present, EEPROM load process does not occur.

3 SBDETECT rwu

1 – EEPROM present, EEPROM load process occurs.

Note that even if a serial EERPOM is not detected following PERST, system software can still

set this bit to enable the serial bus interface. For more information on system software setting

the bit, see section 1.9.4.

This field is reset with PERST.

2 RSVD r Reserved. When read, this bit returns zero.

Serial bus error. This bit is set when an error occurs during a software-initiated serial bus

cycle.

0 – No error

1 SB_ERR rc

1 – Serial bus error

This field is reset with PERST.

Serial EEPROM load error. This bit is set when an error occurs while downloading registers

from a serial EEPROM.

0 – No error

0 ROM_ERR rc

1 – EEPROM load error

This field is reset with PERST.

4.2.59 Upstream Port Link PM Latency Register

This read/write register is used to program L0s and L1 exit latencies for the upstream port.

PCI register offset: B4h

Default value: 0024h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0

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