Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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4.3.67 Uncorrectable Error Mask Register ......................................................................... 122

4.3.68 Uncorrectable Error Severity Register ...................................................................... 123

4.3.69 Correctable Error Status Register ........................................................................... 124

4.3.70 Correctable Error Mask Register ............................................................................ 125

4.3.71 Advanced Error Capabilities and Control Register ....................................................... 126

4.3.72 Header Log Register .......................................................................................... 126

5 PCI Hot Plug Implementation Overview .............................................................................. 128

5.1 PCI Hot Plug Architecture Overview .................................................................................. 128

5.2 PCI Hot Plug Timing ..................................................................................................... 130

5.2.1 Power-Up Cycle ............................................................................................... 130

5.2.1.1 NonPCI Hot Plug Power-Up Cycle ............................................................. 130

5.2.1.2 PCI Hot Plug Power-Up Cycle With PWRGDn Feedback .................................. 130

5.2.1.3 PCI Hot Plug Power-Up Cycle With No PWRGDn Feedback .............................. 130

5.2.2 Power-Down Cycles .......................................................................................... 131

5.2.2.1 Normal Power-Down ............................................................................. 131

5.2.2.2 Surprise Removal ................................................................................ 131

5.2.2.3 PWRGDn De-Assertion .......................................................................... 132

5.2.3 PMI_Turn_Off and PME_To_Ack Messages .............................................................. 132

5.2.4 Debounce Circuits ............................................................................................ 133

5.2.5 HP_INTX Pin .................................................................................................. 133

6 Electrical Characteristics .................................................................................................. 134

6.1 Absolute Maximum Ratings ............................................................................................. 134

6.2 Recommended Operating Conditions ................................................................................. 134

6.3 PCI Express Differential Transmitter Output Ranges ............................................................... 135

6.4 PCI Express Differential Receiver Input Ranges .................................................................... 136

6.5 PCI Express Differential Reference Clock Input Ranges ........................................................... 137

6.6 PCI Express Reference Clock Output Requirements ............................................................... 138

6.7 3.3-V I/O Electrical Characteristics .................................................................................... 139

6.8 POWER CONSUMPTION .............................................................................................. 139

6.9 THERMAL CHARACTERISTICS ...................................................................................... 139