Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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Table 4-28. Bit Descriptions – Link Capabilities Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Maximum link width. This field is encoded 000001b to indicate that the device only supports
9:4 MLW r
an x1 PCI Express link.
Maximum link speed. This field is encoded 0001b to indicate that the device supports a
3:0 MLS r
maximum link speed of 2.5 Gb/s.
4.2.53 Link Control Register
The Link Control register is used to control link-specific behavior.
PCI register offset: A0h
Register type: Read/Write; Read Only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-29. Bit Descriptions – Link Control Register
BIT FIELD NAME ACCESS DESCRIPTION
15:9 RSVD r Reserved. When read, these bits return zeros.
Clock power management enable. When CLKREQ support is enabled, the EP_LI_LAT field in
the Upstream Ports Link PM Latency register increases due to link PLL locking requirements.
8 CPM_EN rw
0 – Disable CLKREQ on upstream port
1 – Enable CLKREQ on upstream port
Extended synch. This bit is used to force the device to extend the transmission of FTS ordered
sets and an extra TS2 when exiting from L1 before entering to L0.
7 ES rw
0 – Normal synch
1 – Extended synch
Common clock configuration. This bit is set when a common clock is provided to both ends of
the PCI Express link. This bit can be used to change the L0s and L1 exit latencies.
6 CCC rw
0 – Reference clock is asynchronous.
1 – Reference clock is synchronous.
5 RL r Retrain link. This bit has no function for upstream ports and is read-only zero.
4 LD r Link disable. This bit has no function for upstream ports and is read-only zero.
Read completion boundary. This bit specifies the minimum size read completion packet that the
XIO3130 can send when breaking a read request into multiple completion packets. This field is
not applicable to XIO3130 switches; i.e., the XIO3130 does not break up completion packets
3 RCB r
and is hardwired to zero.
0 – 64 bytes
1 – 128 bytes
2 RSVD r Reserved. When read, this bit returns zero.
Active state link PM control. This field is used to enable and disable active state PM.
00 – Active state PM disabled
1:0 ASLPMC rw 01 – L0s entry enabled
10 – Reserved
11 – L0s and L1 entry enable
58 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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